ShiboSoftwareDev/solar-battery-charger-module

FABRICATION.md

# Fabrication and bring-up notes

## JLCPCB order configuration

Upload `fabrication/solar-battery-charger-gerbers.zip` for PCB manufacture. Use these settings:

- 2 layers, FR-4, 66.12 × 57.00 mm
- 1.2 mm finished thickness
- **1 oz finished outer copper**; do not change to 2 oz
- Black solder mask and white silkscreen
- ENIG surface finish
- 0.15 mm minimum via-hole option
- JLCPCB via-in-pad process: epoxy filled and capped (copper-paste filled and capped is also acceptable)
- Plated edges enabled; do not select HASL
- 100% flying-probe electrical test
- No V-scoring; preserve the supplied routed outline
- Engineering review requested before production

Paste this into the PCB order remark:

> Preserve the supplied Edge_Cuts outline. Eight intentional exposed top/bottom copper contacts meet the routed left/right edges around semicircular openings. Plate these contact-bearing edges and finish them with ENIG. Use filled-and-capped 0.15/0.35 mm via-in-pad. Do not pull copper back from the eight edge contacts. Please stop for clarification rather than modifying the outline or contacts.

JLCPCB currently lists 0.10/0.10 mm trace/space for 2-layer 1 oz copper, 0.15 mm minimum drilling, 0.15–0.55 mm compatibility for filled-and-capped via-in-pad, and plated-edge support with ENIG. The source pages are:

- https://jlcpcb.com/capabilities/pcb-capabilities
- https://jlcpcb.com/help/article/jlcpcb-copper-weight

This PCB intentionally uses 0.10 mm local routing clearance. JLCPCB's 2 oz minimum is 0.16/0.16 mm, so ordering 2 oz would make this release noncompliant.

## Assembly upload

Enable top-side PCBA and upload:

- BOM: `fabrication/solar-battery-charger-assembly-bom.csv`
- CPL/PnP: `fabrication/solar-battery-charger-pick-and-place.csv`

The files contain 60 components and 34 unique LCSC codes. Confirm that every BOM line maps to the exact LCSC code and footprint shown before payment; do not accept silent substitutions for the three ICs, Q12, either inductor, either shunt, or either connector.

`J_SOLAR` is the only through-hole component. Select the service option that includes THT/manual soldering. `J_BAT` and all other purchased parts are top-side SMT. `J_CTRL` and `J_IO` are PCB copper contacts, not purchasable components, and are deliberately absent from the assembly BOM and PnP.

The positive-stock snapshot is `fabrication/parts-availability-2026-08-17.csv`. Stock is not reserved by the file and can change; the JLCPCB parts-confirmation page is the final authority at checkout.

## Operating limits and pinout

Use a panel with Vmp near 17.8 V and keep its worst-case cold open-circuit voltage below the BQ24650 limit. A panel rated at least about 10–12 W is needed to approach the 2 A charge setting under useful illumination.

| Connector | Pin | Signal | Notes |
|---|---:|---|---|
| J_SOLAR | 1 | SOLAR+ | 21 V-class panel input |
| J_SOLAR | 2 | GND | Solar return |
| J_BAT | 1 | BAT+ | Protected 1S Li-ion positive |
| J_BAT | 2 | NTC | External 10 kΩ 103AT-compatible thermistor |
| J_BAT | 3 | BAT- | Battery negative, gauge-shunt side |
| J_CTRL | 1 | CHARGE_DISABLE | Active high |
| J_CTRL | 2 | OUT_EN | Active high; defaults low |
| J_CTRL | 3 | ALM | STC3115 open-drain alarm, pulled to 3.3 V |
| J_CTRL | 4 | GND | System ground |
| J_IO | 1 | 3V3 | Regulated output |
| J_IO | 2 | GND | System ground |
| J_IO | 3 | SDA | Gauge I²C data |
| J_IO | 4 | SCL | Gauge I²C clock |

## Assembly constraints

- Keep exact BOM assignments for the three ICs, dual MOSFET, inductors, and current shunts.
- Do not substitute TPS63030/TPS63031 variants without rechecking fixed-output feedback behavior.
- The 0 Ω Kelvin/ground/mode/input links are intentional; install all of them.
- Confirm the battery cable order is `BAT+ / NTC / BAT-`; common two-wire JST battery leads are incompatible.
- Use a protected 1S cell. This board is not a certified battery pack-protection system.

## First-article bring-up

1. Inspect QFN/DFN/SON joints, plated edge contacts, and filled/capped thermal vias.
2. With no battery, power from a current-limited bench supply and check for input shorts; then verify BQ24650 VREF and REGN.
3. Attach a protected 1S pack with a known 10 kΩ NTC and a conservative source current limit.
4. Verify input-voltage regulation near 17.8 V and charge-current regulation near 2 A.
5. Verify 4.2 V regulation, termination behavior, and temperature inhibition.
6. Assert `OUT_EN`; verify 3.3 V across the intended battery/load range and perform thermal testing.
7. Calibrate the STC3115 in firmware against the installed cell and 5 mΩ shunt.

The CAD package is orderable, but CAD checks cannot prove analog loop stability, thermal margin, battery safety, EMC, or assembly quality. Qualify a first article before volume production or unattended charging.