ShiboSoftwareDev/am625sip-linux-board

This code defines the physical footprint and pin layout for an AM625 System-in-Package (SIP) component, detailing pad positions, pin labels, and package outline for hardware integration.

Version
1.0.24
License
unset
Stars
0

subcircuits/power-input.tsx

import { B2B_PH_K_S_LF__SN_ } from "../imports/B2B_PH_K_S_LF__SN_"

const GroundBoundaryPad = () => (
  <chip
    name="X_GND"
    pcbX={-14}
    pcbY={-1.2}
    noSchematicRepresentation
    footprint={
      <footprint>
        <platedhole
          portHints={["pin1", "GND"]}
          shape="circle"
          holeDiameter="0.3mm"
          outerDiameter="0.8mm"
        />
      </footprint>
    }
  />
)

export const PowerInputSubcircuit = () => (
  <subcircuit
    name="POWER_INPUT"
    pcbX={29.5}
    pcbY={-31.7}
    autorouter="default"
  >
    <B2B_PH_K_S_LF__SN_
      name="J2"
      pcbX={9.5}
      pcbY={0}
      pcbRotation={180}
    />
    <fuse
      name="F1"
      currentRating="2A"
      voltageRating="12V"
      footprint="1206"
      supplierPartNumbers={{ jlcpcb: ["C883135"] }}
      pcbX={3.7}
      pcbY={0}
    />
    <capacitor
      name="C64"
      capacitance="47uF"
      maxVoltageRating="6.3V"
      footprint="1206"
      supplierPartNumbers={{ jlcpcb: ["C68361"] }}
      pcbX={-1}
      pcbY={0}
      pcbRotation={180}
    />
    <capacitor
      name="C65"
      capacitance="100nF"
      maxVoltageRating="16V"
      footprint="0402"
      supplierPartNumbers={{ jlcpcb: ["C1525"] }}
      pcbX={-5}
      pcbY={0}
      pcbRotation={180}
    />
    <resistor
      name="R23"
      resistance="0"
      footprint="1206"
      supplierPartNumbers={{ jlcpcb: ["C5127787"] }}
      pcbX={-9.5}
      pcbY={0}
      pcbRotation={180}
    />
    <GroundBoundaryPad />

    <trace
      name="POWER_INPUT_RAW"
      from=".J2 > .pin1"
      to=".F1 > .pin2"
      width="0.8mm"
    />
    <trace
      name="POWER_INPUT_RETURN"
      from=".J2 > .pin2"
      to=".X_GND > .pin1"
      width="0.8mm"
    />
    <trace
      name="POWER_INPUT_FUSED"
      from=".F1 > .pin1"
      to=".C64 > .pin1"
      width="0.8mm"
    />
    <trace
      name="POWER_INPUT_CERAMIC"
      from=".C65 > .pin1"
      to=".C64 > .pin1"
      width="0.5mm"
    />
    <trace
      name="POWER_INPUT_BULK_GND"
      from=".C64 > .pin2"
      to=".X_GND > .pin1"
      width="0.5mm"
    />
    <trace
      name="POWER_INPUT_CERAMIC_GND"
      from=".C65 > .pin2"
      to=".X_GND > .pin1"
      width="0.3mm"
    />
    <trace
      name="POWER_INPUT_LOCAL_RAIL"
      from=".C64 > .pin1"
      to=".R23 > .pin1"
      width="0.5mm"
    />
    <silkscreentext
      text="3V3 IN"
      pcbX={7.5}
      pcbY={4.2}
      fontSize="0.9mm"
      anchorAlignment="center"
    />
  </subcircuit>
)