ShiboSoftwareDev/am625sip-linux-board
This code defines the physical footprint and pin layout for an AM625 System-in-Package (SIP) component, detailing pad positions, pin labels, and package outline for hardware integration.
- Version
- 1.0.24
- License
- unset
- Stars
- 0
subcircuits/cache/microsd.circuit.json
PCB
Schematic
[
{
"type": "source_group",
"source_group_id": "source_group_0",
"is_subcircuit": true,
"was_automatically_named": true,
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_0",
"name": "DAT2",
"pin_number": 1,
"port_hints": [
"DAT2",
"pin1",
"1"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_1",
"name": "DAT3_CD",
"pin_number": 2,
"port_hints": [
"DAT3_CD",
"pin2",
"2"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_2",
"name": "CMD",
"pin_number": 3,
"port_hints": [
"CMD",
"pin3",
"3"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_port",
"source_port_id": "source_port_3",
"name": "VDD",
"pin_number": 4,
"port_hints": [
"VDD",
"pin4",
"4"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_4",
"name": "CLK",
"pin_number": 5,
"port_hints": [
"CLK",
"pin5",
"5"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_port",
"source_port_id": "source_port_5",
"name": "VSS",
"pin_number": 6,
"port_hints": [
"VSS",
"pin6",
"6"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_6",
"name": "DAT0",
"pin_number": 7,
"port_hints": [
"DAT0",
"pin7",
"7"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_port",
"source_port_id": "source_port_7",
"name": "DAT1",
"pin_number": 8,
"port_hints": [
"DAT1",
"pin8",
"8"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_8",
"name": "CD",
"pin_number": 9,
"port_hints": [
"CD",
"pin9",
"9"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_9",
"name": "GND1",
"pin_number": 10,
"port_hints": [
"GND1",
"pin10",
"10"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_10",
"name": "GND2",
"pin_number": 11,
"port_hints": [
"GND2",
"pin11",
"11"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_11",
"name": "GND3",
"pin_number": 12,
"port_hints": [
"GND3",
"pin12",
"12"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_port",
"source_port_id": "source_port_12",
"name": "GND4",
"pin_number": 13,
"port_hints": [
"GND4",
"pin13",
"13"
],
"source_component_id": "source_component_0",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_component",
"source_component_id": "source_component_0",
"ftype": "simple_chip",
"name": "J1",
"manufacturer_part_number": "XKTF_N02_N",
"supplier_part_numbers": {
"jlcpcb": [
"C381084"
]
},
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_13",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_port",
"source_port_id": "source_port_14",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_1",
"ftype": "simple_resistor",
"name": "R5",
"supplier_part_numbers": {
"jlcpcb": [
"C473048"
]
},
"resistance": 10000,
"display_resistance": "10kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_15",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"anode",
"pos",
"left",
"1"
],
"source_component_id": "source_component_2",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_port",
"source_port_id": "source_port_16",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"cathode",
"neg",
"right",
"2"
],
"source_component_id": "source_component_2",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_2",
"ftype": "simple_resistor",
"name": "R6",
"supplier_part_numbers": {
"jlcpcb": [
"C473048"
]
},
"resistance": 10000,
"display_resistance": "10kΩ",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_17",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_3",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_18",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_3",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_component",
"source_component_id": "source_component_3",
"ftype": "simple_capacitor",
"name": "C22",
"supplier_part_numbers": {
"jlcpcb": [
"C1525"
]
},
"capacitance": 1e-7,
"max_voltage_rating": 10,
"max_decoupling_trace_length": 1,
"display_capacitance": "100nF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_19",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"pos",
"anode",
"1",
"left"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_port",
"source_port_id": "source_port_20",
"name": "pin2",
"pin_number": 2,
"port_hints": [
"pin2",
"neg",
"cathode",
"2",
"right"
],
"source_component_id": "source_component_4",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_component",
"source_component_id": "source_component_4",
"ftype": "simple_capacitor",
"name": "C23",
"supplier_part_numbers": {
"jlcpcb": [
"C52923"
]
},
"capacitance": 0.000001,
"max_voltage_rating": 10,
"max_decoupling_trace_length": 1,
"display_capacitance": "1uF",
"are_pins_interchangeable": true,
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_21",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_5",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_5",
"ftype": "simple_chip",
"name": "X_CMD",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_22",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_6",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_6",
"ftype": "simple_chip",
"name": "X_DAT0",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_23",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_7",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_component",
"source_component_id": "source_component_7",
"ftype": "simple_chip",
"name": "X_CLK",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_24",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_8",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_component",
"source_component_id": "source_component_8",
"ftype": "simple_chip",
"name": "X_SOC_CMD",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_25",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_9",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_component",
"source_component_id": "source_component_9",
"ftype": "simple_chip",
"name": "X_SOC_DAT0",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_26",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_10",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_component",
"source_component_id": "source_component_10",
"ftype": "simple_chip",
"name": "X_SOC_CLK",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_27",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_11",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_component",
"source_component_id": "source_component_11",
"ftype": "simple_chip",
"name": "X_VDD",
"source_group_id": "source_group_0"
},
{
"type": "source_port",
"source_port_id": "source_port_28",
"name": "pin1",
"pin_number": 1,
"port_hints": [
"pin1",
"1"
],
"source_component_id": "source_component_12",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "source_component",
"source_component_id": "source_component_12",
"ftype": "simple_chip",
"name": "X_GND",
"source_group_id": "source_group_0"
},
{
"type": "source_board",
"source_board_id": "source_board_0",
"source_group_id": "source_group_0"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_0",
"connected_source_port_ids": [
"source_port_24",
"source_port_21"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "MICROSD_SOC_CMD_ENTRY",
"display_name": ".X_SOC_CMD > .pin1 to .X_CMD > .pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_1",
"connected_source_port_ids": [
"source_port_25",
"source_port_22"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "MICROSD_SOC_DAT0_ENTRY",
"display_name": ".X_SOC_DAT0 > .pin1 to .X_DAT0 > .pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_2",
"connected_source_port_ids": [
"source_port_26",
"source_port_23"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "MICROSD_SOC_CLK_ENTRY",
"display_name": ".X_SOC_CLK > .pin1 to .X_CLK > .pin1",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_3",
"connected_source_port_ids": [
"source_port_21",
"source_port_2",
"source_port_13"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "MICROSD_CMD",
"max_length": 30,
"display_name": ".X_CMD > .pin1 to .J1 > .CMD",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net0"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_4",
"connected_source_port_ids": [
"source_port_22",
"source_port_6",
"source_port_15"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "MICROSD_DAT0",
"max_length": 30,
"display_name": ".X_DAT0 > .pin1 to .J1 > .DAT0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_5",
"connected_source_port_ids": [
"source_port_23",
"source_port_4"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "MICROSD_CLK_ENTRY",
"max_length": 30,
"display_name": ".X_CLK > .pin1 to .J1 > .CLK",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net2"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_6",
"connected_source_port_ids": [
"source_port_27",
"source_port_14",
"source_port_16",
"source_port_3",
"source_port_17",
"source_port_19"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "MICROSD_VDD",
"max_length": 40,
"display_name": ".X_VDD > .pin1 to .R5 > .pin2",
"min_trace_thickness": 0.2,
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "source_trace",
"source_trace_id": "source_trace_7",
"connected_source_port_ids": [
"source_port_28",
"source_port_18",
"source_port_20",
"source_port_5",
"source_port_9",
"source_port_10",
"source_port_11",
"source_port_12"
],
"connected_source_net_ids": [],
"subcircuit_id": "subcircuit_source_group_0",
"name": "MICROSD_GND",
"max_length": 40,
"display_name": ".X_GND > .pin1 to .C22 > .pin2",
"min_trace_thickness": 0.3,
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "schematic_component",
"schematic_component_id": "schematic_component_0",
"center": {
"x": 0,
"y": 0
},
"rotation": 0,
"size": {
"width": 1.3,
"height": 1.6
},
"pin_spacing": 0.2,
"port_labels": {
"pin1": "DAT2",
"pin2": "DAT3_CD",
"pin3": "CMD",
"pin4": "VDD",
"pin5": "CLK",
"pin6": "VSS",
"pin7": "DAT0",
"pin8": "DAT1",
"pin9": "CD",
"pin10": "GND1",
"pin11": "GND2",
"pin12": "GND3",
"pin13": "GND4"
},
"source_component_id": "source_component_0",
"schematic_group_id": "schematic_group_0"
},
{
"type": "schematic_component",
"schematic_component_id": "schematic_component_1",
"center": {
"x": -0.7500000000000004,
"y": 2.1399999999999997
},
"size": {
"width": 0.6,
"height": 0.65
},
"source_component_id": "source_component_1",
"is_box_with_pins": true,
"symbol_name": "boxresistor_left",
"symbol_display_value": "10kΩ",
"schematic_group_id": "schematic_group_0"
},
{
"type": "schematic_component",
"schematic_component_id": "schematic_component_2",
"center": {
"x": -2.0500000000000003,
"y": 1.2600000000000005
},
"size": {
"width": 0.6,
"height": 0.65
},
"source_component_id": "source_component_2",
"is_box_with_pins": true,
"symbol_name": "boxresistor_left",
"symbol_display_value": "10kΩ",
"schematic_group_id": "schematic_group_0"
},
{
"type": "schematic_component",
"schematic_component_id": "schematic_component_3",
"center": {
"x": -2.12,
"y": -1.4699999999999993
},
"size": {
"width": 0.65,
"height": 0.6
},
"source_component_id": "source_component_3",
"is_box_with_pins": true,
"symbol_name": "capacitor_down",
"symbol_display_value": "100nF",
"schematic_group_id": "schematic_group_0"
},
{
"type": "schematic_component",
"schematic_component_id": "schematic_component_4",
"center": {
"x": -2.12,
"y": -0.09999999999999964
},
"size": {
"width": 0.65,
"height": 0.6
},
"source_component_id": "source_component_4",
"is_box_with_pins": true,
"symbol_name": "capacitor_down",
"symbol_display_value": "1uF",
"schematic_group_id": "schematic_group_0"
},
{
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"y": -2.6909440996099074,
"width": 0.19064,
"layer": "top"
},
{
"route_type": "wire",
"x": -2.4499657,
"y": 6.849872,
"width": 0.19064,
"layer": "top",
"end_pcb_port_id": "pcb_port_11"
}
],
"subcircuit_id": "subcircuit_source_group_0",
"source_trace_id": "source_trace_7",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "pcb_trace",
"pcb_trace_id": "microsd__source_trace_7_mst6_0",
"connection_name": "source_trace_7",
"connectsTo": [
"pcb_port_28",
"pcb_port_9"
],
"route": [
{
"route_type": "wire",
"x": -14,
"y": -14,
"width": 0.3,
"layer": "top",
"start_pcb_port_id": "pcb_port_28"
},
{
"route_type": "wire",
"x": -8.7,
"y": -14,
"width": 0.3,
"layer": "top"
},
{
"route_type": "wire",
"x": -2.449965700000001,
"y": -7.750048,
"width": 0.3,
"layer": "top",
"end_pcb_port_id": "pcb_port_9"
}
],
"subcircuit_id": "subcircuit_source_group_0",
"source_trace_id": "source_trace_7",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "pcb_via",
"pcb_via_id": "pcb_via_0",
"pcb_trace_id": "microsd__source_trace_4_mst0_0",
"x": -9.440001435176484,
"y": 4.250000066340262,
"hole_diameter": 0.1,
"outer_diameter": 0.24,
"layers": [
"top",
"inner1",
"inner2",
"bottom"
],
"from_layer": "inner1",
"to_layer": "top",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "pcb_via",
"pcb_via_id": "pcb_via_1",
"pcb_trace_id": "microsd__source_trace_4_mst0_0",
"x": -4.53,
"y": 9.879998797575075,
"hole_diameter": 0.1,
"outer_diameter": 0.24,
"layers": [
"top",
"inner1",
"inner2",
"bottom"
],
"from_layer": "top",
"to_layer": "inner1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net1"
},
{
"type": "pcb_via",
"pcb_via_id": "pcb_via_2",
"pcb_trace_id": "microsd__source_trace_6_mst4_0",
"x": -3.5714825473810885,
"y": 10.498517452618911,
"hole_diameter": 0.1,
"outer_diameter": 0.24,
"layers": [
"top",
"inner1",
"inner2",
"bottom"
],
"from_layer": "top",
"to_layer": "inner1",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "pcb_via",
"pcb_via_id": "pcb_via_3",
"pcb_trace_id": "microsd__source_trace_6_mst4_0",
"x": -2.9800288575671203,
"y": -0.5800353421660938,
"hole_diameter": 0.1,
"outer_diameter": 0.24,
"layers": [
"top",
"inner1",
"inner2",
"bottom"
],
"from_layer": "inner1",
"to_layer": "top",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net3"
},
{
"type": "pcb_via",
"pcb_via_id": "pcb_via_4",
"pcb_trace_id": "microsd__source_trace_7_mst3_0",
"x": -2.4499959440455985,
"y": 7.769871904472117,
"hole_diameter": 0.1,
"outer_diameter": 0.24,
"layers": [
"top",
"inner1",
"inner2",
"bottom"
],
"from_layer": "inner2",
"to_layer": "top",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
},
{
"type": "pcb_via",
"pcb_via_id": "pcb_via_5",
"pcb_trace_id": "microsd__source_trace_7_mst3_0",
"x": 2.4800016696288423,
"y": 10.2,
"hole_diameter": 0.1,
"outer_diameter": 0.24,
"layers": [
"top",
"inner1",
"inner2",
"bottom"
],
"from_layer": "top",
"to_layer": "inner2",
"subcircuit_id": "subcircuit_source_group_0",
"subcircuit_connectivity_map_key": "unnamedsubcircuitsubcircuit_source_group_0_connectivity_net4"
}
]
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