ShiboSoftwareDev/MSP-EXP430FR2433

README.md

# MSP-EXP430FR2433 compatible LaunchPad — tscircuit edition

This repository contains a four-layer tscircuit implementation of a TI
MSP-EXP430FR2433-style LaunchPad. It includes the MSP430FR2433 target, a
USB-protected MSP430F5528 eZ-FET-style debugger/UART section, removable
debug/power isolation links, BoosterPack headers, buttons, LEDs, a 32.768 kHz
crystal, external-power access, test points, and an optional supercapacitor.

## Important design differences

- This is an electrically compatible reimplementation, not a geometric clone
  of TI's PCB.
- TI's EnergyTrace switch-mode measurement supply is replaced with a protected
  TLV70033 3.3 V LDO. Programming, SBW debug, USB UART, and board power remain;
  EnergyTrace current measurement does not.
- The MSP430F5528 must be programmed with compatible eZ-FET firmware through
  `J_DBG_PROG` before the USB debugger/UART section can enumerate and operate.
- `C_SUPERCAP` is DNP by default. Install all seven `J_ISO_*` shunts for normal
  LaunchPad operation.

## Manufacturing package

- Board: 54 mm × 86 mm, 1.6 mm FR-4 recommended
- Copper order: F.Cu / In1.Cu (GND plane) / In2.Cu / B.Cu
- Minimum routed trace: 0.15 mm
- Routed vias: 0.30 mm drill, 0.45 mm copper pad
- Solder mask, paste, and silkscreen: top and bottom only

The PCB fabrication upload is
`fabrication/msp-exp430fr2433-4layer-gerbers.zip`. It was generated directly
from the validated Circuit JSON with `circuit-json-to-gerber` 0.0.94 and
contains four copper files, top/bottom mask, paste and silkscreen, the outline,
six plated drill-span files, and one NPTH file. Inner copper contains plated
annuli but no solder-mask geometry.

The default autorouter created 89 blind or buried vias and 54 through vias.
Therefore this package is fabrication-ready only for a board house that accepts
the six declared L1-L2, L1-L3, L1-L4, L2-L3, L2-L4 and L3-L4 drill spans. It is
not a standard low-cost through-via-only four-layer order. tscircuit currently
does not expose an obvious default-autorouter option to force every via to span
F.Cu through B.Cu.

`fabrication/bom.csv` and `fabrication/pick-and-place.csv` are separate assembly
files. The placement coordinates use the same original coordinate system as the
native Gerbers. The LCSC numbers remain candidates: verify package dimensions,
ratings, availability, and LED color before purchasing assembly.

## Rebuilding

The release dependencies are pinned exactly:

- `tscircuit` 0.0.2311 (`@tscircuit/cli` 0.1.1910, core 0.0.1665)
- `circuit-json-to-gerber` 0.0.94
- `circuit-json-to-kicad` 0.0.173

```sh
bun install --frozen-lockfile
bun run typecheck
bun run build
bun run export:gerbers
bun run export:kicad
bun run export:assembly
```

Zip the files in `fabrication/gerbers` after regenerating them. The direct
export scripts are intentional: the latest top-level `tsci export` bundle still
uses an older converter than the directly pinned packages.

## Verification results

- TypeScript: pass
- Default autorouter: 136 routed traces, 0 jumpers, 0 router-reported errors
- Generated Circuit JSON: 0 PCB/source errors, 152 total PCB traces
- Vias: 143, all 0.30 mm drill / 0.45 mm pad
- Netlist check: 0 errors, 0 warnings
- Placement check/DRC: 0 errors, 0 warnings
- `tsci check shorts --mode gerber --layer all`: no shorts detected
- KiCad 10: latest `.kicad_pcb` loads and renders; all five bottom components
  are emitted on B.Cu, confirming circuit-json-to-kicad PR 412 is effective

The KiCad export is a review artifact, not the fabrication source. The converter
does not carry tscircuit's 0.15 mm trace, 0.45/0.30 mm via, 0.10 mm clearance,
or blind/buried-via manufacturing rules into a KiCad project, so KiCad's stock
DRC reports violations against its unrelated defaults.

## Remaining tscircuit limitations observed

1. The default autorouter can report `errors=0` and still create a final
   clearance violation. Its result also changes between runs. Sensitive USB,
   crystal, UART, power and GND escapes are explicitly routed here, and Circuit
   JSON DRC—not the router status—is the release gate.
2. `tsci build` still exits with status 0 when Circuit JSON contains PCB errors.
3. `tsci check shorts --mode pcb --layer all` fails after rendering with
   `layerCanvas.getContext is not a function`. Gerber mode works and passes.
4. `tsci export --format gerbers` in tscircuit 0.0.2311 uses the bundled Gerber
   converter. The project pins 0.0.94 directly to include the inner-layer plated
   copper fix. That 0.0.94 package still writes `0.0.93` in its Gerber metadata.
5. The `circuit-to-gerber` binary shipped by 0.0.94 cannot start because its
   `archiver` runtime dependency is missing. `scripts/export-latest-gerbers.mjs`
   uses the supported library API instead.
6. The latest top-level tscircuit build still rejects JLCPCB C11337's blank
   `fontStyle`. The explicit verified SOT-23-5 footprint and pin map keep the LDO
   electrically and geometrically defined, but the parts-engine enrichment
   warning remains.
7. Supplier enrichment reports footprint-IoU mismatches for 27 generic
   0402/0603/header candidates. They do not change PCB geometry, but the BOM is
   not approved for turnkey assembly until those candidates are reviewed.
8. The native assembly SVG has severe reference-text overlaps on this dense
   board. Use the BOM/PnP files and PCB render for manufacturing review.
9. The default four-layer autorouter uses blind and buried vias, and its public
   board/autorouter props do not currently offer a through-via-only switch.

The board is electrically routed and its native Gerber package passes the
available Gerber shorts gate. The remaining release decision is manufacturing
process: select an HDI-capable fabricator for the declared drill spans, or
manually reroute to through vias before ordering from a standard four-layer
service.