MustafaMulla29/stride-pedometer

This code defines schematic symbols and 3D footprints for various hardware components such as antennas, sensors, regulators, and connectors used in electronic circuit design.

Version
1.0.4
License
unset
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0

review/VALIDATION.md

PCBPCB preview for review/VALIDATION.md
# Shorts and routing verification — 2026-09-07

**The corrected main project passes `bunx tsci check shorts`, with zero compiled routing errors and zero separate routing findings. Fabrication is not released.**

## What was wrong

The earlier native `simplify` phase produced zero ordinary DRC records but introduced two routes that changed layers without a physical via at the transition. The Gerber shorts check detected CHG_CE touching the inner1 ground pour near R5, around (8.692, 8.196) mm. The earlier zero-DRC claim was incomplete. `shorts-before-prebuilt.txt` records the failed check.

## Exact repair

- Removed the final native `simplify` phase and its explicit phase-1 net/trace assignments, restoring the original two-phase native routing structure.
- Moved **R5 right by 0.2 mm**, from (8.7, 8.7) to **(8.9, 8.7) mm**, retaining its 90° rotation.
- Rebuilt all routing from source with the default tscircuit autorouter.
- Added detection of invalid wire-layer transitions and retained compiled errors in the validation script. `bun run routing` now also invokes the Gerber shorts check.

Removing simplification alone eliminated the short but restored one via-clearance violation. The R5 move lets the native router produce a result that passes both checks. No schematic connections, footprints, other component positions, or clearance rules changed in this repair. The chip-level design, through vias, 40 × 35 mm outline, four layers, and 0.8 mm thickness remain unchanged.

```tsx
<autoroutingphase phaseIndex={0} name="U2_inner_signals"
  autorouter={{allowViaInPad:true}}/>
<autoroutingphase name="remaining_board"/>
```

There is no custom algorithm, saved route replay, trace hint, breakout, dependency patch, or explicit `<via />` element. Native routing inserts the necessary vias. Minimum trace/pad clearance remains 0.09 mm; via hole/pad diameters remain 0.15 / 0.25 mm. The paused 0.30 / 0.45 mm settings were not applied. The eight RF links remain declarative trace elements, whose generated geometry must still be reviewed.

## Checks on the actual rebuilt project

| Check | Result |
|---|---|
| TypeScript | Pass |
| Logical netlist | Pass |
| Semantic connectivity versus one-error baseline | Identical |
| Pad comparison | Only the two R5 lands moved 0.2 mm |
| Schematic placement | No actionable findings |
| PCB placement | 0 errors, 0 warnings |
| Compiled circuit error records | 0 |
| Separate routing, clearance, connectivity, thickness, and off-board checks | 0 findings |
| Invalid wire-layer transitions | 0 |
| `bunx tsci check shorts` on source | No shorts detected |
| Gerber shorts on built JSON, all four layers | No shorts detected |
| Gerber shorts at 64 pixels/mm, all four layers | No shorts detected |
| PCB traces | 183 |
| Physical via records / unique locations | 162 / 149 |
| Population | 78 design items; 66 proposed PCBA placements |

The isolated placement trial passed before the same source was promoted and rebuilt in the main project. An initial main build reached the 600-second timeout during DRC repair. Native routing cache entries were archived, and the unchanged source was rebuilt with diagnostics enabled from an empty routing cache. Both phase inputs matched the passing trial. No cache entries or routes were transplanted from the trial. Build/validation logs are saved here. `routing-change.json` includes source/circuit hashes and the before/after result; `source-change.diff` shows the source edit. Through-via normalization only corrects export span metadata on existing all-layer vias.

Runtime versions are unchanged: tscircuit 0.0.2465, core 0.0.1854, capacity-autorouter 0.0.885. Package version remains 1.0.3. Symbol/pin metadata, reference-prefix, unnamed-trace, and courtyard warnings remain visible in `validation.json`; React list-key warnings remain in logs.

## Limits

These checks establish the reported routing result under the project's current rules and the shorts checker's bitmap resolution. They do not establish full fabricator DFM, RF/clock performance, or a functioning product. `FUNCTIONAL-AUDIT.md` records the remaining U6 footprint issue, analog-layout review, display supply margin, missing firmware, assembly needs, and unmeasured battery life. No fabrication release or order has been made; fabrication/KiCad archives have not been regenerated for this repair.