MustafaMulla29/stride-pedometer

review/ROUTING-TRIALS.md

PCB

# Native autorouter trials — 2026-09-07

The retained implementation now uses the original two native routing phases with **R5 shifted right by 0.2 mm**. It passes the source and prebuilt Gerber shorts checks, strengthened routing checks, and compiled error checks. The previous native simplification result was withdrawn after the separate shorts check exposed a short and invalid layer transitions.

Tests used the original 40 × 35 mm, four-layer, 0.8 mm board. No custom routing algorithm, dependency patch, saved route replay, or explicit `<via />` element was used. Runs that failed routing, lost connectivity, or changed schematic connectivity were rejected even when the CLI exited successfully.

| Trial | Result |
|---|---|
| Original tscircuit 0.0.2464 default routing | 8 findings, all around U2 |
| tscircuit 0.0.2465 default Pipeline 9, unchanged placement | 9 findings |
| Native U2 breakout on the newer runtime | 14 findings around U2; rejected |
| Pipeline 9, four U2 nets first, unchanged placement | 11 findings; U2 cleared, conflicts near U1/C19 |
| Above plus C19 rotation | 6 findings |
| Above plus U1/C19 placement changes | 4 findings |
| Above plus C18 relocation/rotation — previous baseline | **1 finding near U1; all U2 findings cleared** |
| Explicit `beta_pipeline7` with routing phases | Router iteration failure; board not fully routed |
| `beta_pipeline9`, `autorouterEffortLevel="100x"`, routing phases | Router could not resolve a conflict involving routes fixed by the earlier phase |
| `beta_pipeline9`, `100x`, whole-board routing | Timed out after 601.8 seconds; no completed circuit |
| Native layer-restricted buses combined with phases | Runtime could not resolve an SRJ connection for the bus; no valid completed routing |
| Larger via margins (0.25 mm hole spacing / 0.12 mm via-to-pad), with placement changes | Routing failed; rejected |
| `allowBlindAndBuriedVias`, original 0.15 / 0.25 mm via hole/pad | 2 findings at one location near C19; not retained |
| Blind/buried vias, 0.15 / 0.30 mm hole/pad, C19 moved | 2 findings at one location near U4; not retained |

## Relevant prop behavior

In the tested runtime, `autorouterVersion="beta_pipeline9"` selects the same implementation as the default Pipeline 9. Selecting it alone is not an improvement. `autorouterEffortLevel="100x"` was tested separately; it increased search time without delivering a clean result.

`autorouter={{preset:"auto_local", allowViaInPad:true}}` is not equivalent to `autorouter={{allowViaInPad:true}}` in this runtime. The installed core's preset resolver drops the extra options for `auto_local`. The selected first phase omits the preset so `allowViaInPad` reaches the built-in local router. Debug routing input confirmed the option was enabled.

Changing `solderMaskColor`, silkscreen visibility, or schematic auto-layout does not address these copper-routing violations. Board dimensions and thickness were kept unchanged. The screenshot's reduced 0.05 mm clearances and 0.10 / 0.20 mm via settings were not adopted.

## HDI implications

Blind/buried-via trials generated both adjacent-layer connections and spans across three copper layers. Such spans require a fabricator-specific HDI construction and drill-stack review. Simply turning on the prop does not establish a fabricable stackup.

JLCPCB's [HDI capability FAQ](https://jlcpcb.com/help/article/hdi-pcb-capabilities-faq) specifies at least a 0.075 mm annular ring for blind and buried vias. That is why the second HDI experiment used a 0.30 mm pad for a 0.15 mm hole, rather than retaining the smaller annular ring. This trial still failed DRC and was not selected. Exact layer spans, dielectric thicknesses, filled/capped vias, component lands, and assembly remain to be reviewed before ordering.

The project remains through-via construction. The independent routing checker retains the original clearance rules and reports zero findings for the selected result; no checks were disabled or waived.

## Final clearance-fix trials

All trials below started from the one-error baseline, using the same installed runtime. They were kept in isolated work directories. Rejected trials were not promoted.

| Trial | Compiled errors / outcome |
|---|---|
| C19 nearer VDDR, first position | PCB placement failed; routing not run |
| R5 moved up | PCB placement failed; routing not run |
| U1 right 0.1 mm | 217 |
| C19 nearer VDDR, lower position | 11 |
| R5 rotated 180° | 11 |
| U1 down 0.1 mm | 12 |
| Regional reroute before the unnumbered phase | 125 |
| Regional reroute after explicit phase 1 | 481 |
| C19 right 0.1 mm | 6 |
| C19 down 0.1 mm | 5 |
| Native V3 route hint | 2 |
| Native V3 hint declared last | 2 |
| Native V3 hint adjusted up | 2 |
| Native CHG_CE route hint | 12 |
| Native CHG_CE hint shifted left | 11 |
| 0.30 mm via pad, unchanged 0.15 mm hole | 35 |
| Final native simplify phase — withdrawn | 0 ordinary compiled errors, but 1 Gerber short and 2 invalid layer transitions |

## Shorts repair trials

All completed trials below used the pinned native autorouter and unchanged clearance rules.

| Trial | Outcome |
|---|---|
| Remove simplify, original R5 position | No shorts; original 1 via-clearance error returned |
| Targeted CHG_CE reroute | 7 compiled errors; rejected |
| Repair U2 nets after simplify | 8 compiled errors; rejected |
| Targeted simplifier with explicit U2 traces | 2 compiled errors and 4 invalid layer transitions; rejected |
| Default native router at 2× effort | 7 compiled errors; rejected |
| No simplify, C19 shifted right 0.05 mm | 13 compiled errors; rejected |
| **No simplify, R5 shifted right 0.2 mm** | **0 compiled errors, 0 routing findings, 0 shorts, 0 invalid layer transitions; retained** |
| Initial main rebuild of retained source | Reached 600-second timeout during DRC repair |
| Main rebuild with native router cache cleared and diagnostics enabled | Pass; phase inputs identical to the isolated trial |

Two redundant trial runs were canceled before producing a final circuit and are not counted as successes or failures. The retained trial passed in isolation and after a fresh main-project build. Logical connectivity was preserved; only the R5 pad positions changed. See `VALIDATION.md` for the full result and its engineering limits.