AnasSarkiz/ble-pedometer

DRC_REPORT.md

# Routed-board validation — zero DRC

Latest audit (2026-09-06): see [PACKAGE_UPDATE_REPORT.md](PACKAGE_UPDATE_REPORT.md). The integrated official exporters now produce **0 incorrect physical drill spans** and exactly **50 fitted BOM/PnP rows**, with package descriptions. The fresh routed export has 0 DRC errors and 0 independent shorts; 28 tests and 4 snapshots pass. Supplier orientation/centroid and CAM sign-off remain outstanding. Publication is authorized for engineering review only, not manufacturing.

Verified 2026-09-05 with pinned tscircuit 0.0.2463, TypeScript 5.9.3 and Bun 1.3.9.

**The validated board has 0 emitted DRC errors and 0 independently detected shorts. Source publication is for engineering review only, not a JLCPCB manufacturing release.**

## Historical validation results

### Green-mask and silkscreen engineering-review revision (2026-09-05)

The latest source replaces long imported/default labels with 58 unique short references and individually reviewed positions. Five SWD function labels are aligned with their pads; the board title and two-line antenna legend remain. Full descriptive source/BOM names, footprint outlines and pin-one marks are preserved. Native `pcbSx` styling controls the replacement; no generated geometry was edited.

- Green solder mask verified in emitted board metadata.
- **25 tests pass**, including four snapshots and positive/negative text-clearance regressions; TypeScript, netlist, placement and schematic-placement checks pass.
- Full build: **0 error records, 40 metadata warnings, 0 independent shorts**.
- **0 conservative text-envelope collisions** with other labels, pads, drills or component courtyards, checked on the routed artifact with `bun scripts/check-silkscreen.ts`.
- Routed traces, vias, pads and holes were compared with the saved zero-DRC route and are byte-for-byte unchanged. The separate fabrication gate still rejects **69 drill-export conflicts**.
- Pre-publication `dist/index/circuit.json` SHA-256: `54d0b123c79875c265d02f8bf430bdbee2b7a781ae424a997a3782d4c4bbbfa7`.

Review image: `dist/silkscreen-review.png`. Checks: `dist/silkscreen-review-final.log`, `dist/silkscreen-build-final.log`, and `dist/silkscreen-fabrication-final.log`. This cleanup is not vendor CAM approval and does not make the board ready to order.

Pre-publication review/build were rerun with the same results; logs are `dist/silkscreen-publish-review.log` and `dist/silkscreen-publish-build.log`. Independent shorts and the dedicated silkscreen check passed again, while all 69 fabrication blockers remain visible.

### Previously published 1.0.5 validation

| Check | Result |
|---|---:|
| Full routed Circuit JSON error records (`*_error`) | **0** |
| Independent Gerber-geometry short check | **0 shorts; pass** |
| TypeScript | Pass |
| Regression tests | **22 passing, 0 failing** |
| Reviewed visual snapshots | 4 passing |
| Source netlist | 0 errors, 0 warnings |
| Source placement | 0 errors, 0 warnings |
| Explicit post-route placement check | 0 errors, 0 warnings |
| Schematic-placement analysis | No reported issues |
| Schematic sheet overflow | 0 warnings |
| Sheets / sections / normal components and test pads | 3 / 8 / 58 |
| Fitted components | 50; excludes 6 test pads and 2 DNP capacitors |
| Routed traces / vias | **166 / 119** |
| Minimum actual via drill / pad | **0.30 / 0.45 mm** |
| Vias listing all four physical copper layers | 119 / 119 |
| Online supplier-footprint lookup failures / mismatch warnings | 0 / 0 |
| Remaining emitted metadata warnings | **40** |
| Conflicting logical drill spans | **69 vias** |
| Separate fabrication geometry gate | **Fails: 69 drill-export conflicts** |

The successful route is recorded in `dist/wson-route-38.log`. A subsequent online supplier verification is recorded in `dist/final-online-verification.log`; its routed traces and vias were compared against the saved offline result and are unchanged. The final short and post-route placement checks were rerun on that online-verified output. Pre-publication review and an online rebuild again passed with the counts above; see `dist/publish-review.log`, `dist/publish-build.log` and `dist/publish-shorts.log`. The unchanged fabrication gate again rejected 69 drill spans in `dist/publish-fabrication.log`.

Final file: `dist/index/circuit.json`.

Pre-publication SHA-256: `b2e87d6bd328a965302b622fd59cf620f00f99e045abe790465953abd8cd69da`.

The hash identifies this exact validation artifact, not a promised reproducible whole-file hash: warning IDs and other build metadata can change. Never rely on the CLI exit code alone; intermediate failed builds returned zero. This result was established by inspecting the emitted records and separately running the short checker.

## Changes that enabled routing

- Retained the 60 × 38 mm, four-layer layout, three ANSI B sheets and eight schematic sections. All 58 normal parts/test pads fit the placement checks.
- Replaced the blocked BQ25150 ball-array charger with the user-approved BQ25186DLHR WSON and independent TPS7A0233DBVR logic regulator. See `CHARGER_BRINGUP.md` for the changed power and firmware requirements.
- Rotated the gauge and moved its BIN resistor; adjusted decouplers and RF spacing. C14 and R11 now face their connected MCU pins.
- Added real, connected, staggered through-via fanouts at congested MCU and charger pins. The VDDR bridge uses explicit native via connection points and bottom-layer copper, preventing redundant escape drills.
- Authored continuous SWD, charger-enable, INT2, SDA pull-up, MCU ground, VDDD, crystal and RF-input routes where automatic branches needed control. Regression tests cover connectivity, layer continuity, actual via sizes and critical route endpoints.
- Used one native `auto_local` board-routing phase. Planning margins are 0.16 mm trace/pad, 0.22 mm via/pad and 0.30 mm drill-hole-edge spacing. Actual solver input was checked to confirm these settings were applied.

The acceptance rules were not relaxed: 0.10 mm minimum trace, 0.09 mm trace/pad, 0.10 mm via/pad and pad/pad, 0.20 mm board edge, and the requested 0.30/0.45 mm via minima. Blind/buried routing remains disabled. No generated geometry, dependencies, DRC filters or thresholds were patched to manufacture a pass.

Automatic fanout and preloaded-trace solver trials that failed were removed. Aborted routing was never counted as zero DRC. See `FANOUT_REVIEW.md` for the retained approach and historical experiments.

## Remaining warnings and release blockers

| Warning category | Count |
|---|---:|
| Reference-designator versus imported primitive convention | 5 |
| Missing courtyards: 16 native via primitives + 6 bare test pads | 22 |
| Underspecified pin metadata | 3 |
| Missing semantic power-pin declarations | 7 |
| Missing semantic ground-pin declarations | 3 |
| **Total** | **40** |

These warnings remain visible. The initial offline run also had 50 failed supplier lookups; online verification cleared those without changing the copper. Supplier availability is not reserved, and successful footprint comparison is not assembly approval.

The obsolete CLI-bundled exporter prioritizes legacy routing endpoints and still creates incorrect spans. The new `export:manufacturing-review` command uses released Gerber 0.0.104, checks the actual full-stack drill output and leaves Circuit JSON unchanged. Its geometry gate checks physical layers; a regression proves legacy transition endpoints do not create blind drilling and duplicate barrel records do not create duplicate drill operations.

Remaining release work: supplier orientation/centroid and CAM review; RF/decoupling/antenna qualification; battery, NTC and display selection; firmware and first-article testing. Silkscreen cleanup, DNP/test-pad exclusion and package-description export are now implemented and tested. No firmware has been delivered or tested in this hardware revision. See `FABRICATION_NOTES.md` and `DESIGN_REVIEW.md`.

**Do not order an older Gerber archive. No new fabrication archive was released.**

## Reproduce

```sh
bun install --frozen-lockfile
bun run check:review
bun run export:schematics
bun run build
bunx tsci check shorts dist/index/circuit.json
bunx tsci check placement dist/index/circuit.json
bun scripts/check-fabrication.ts dist/index/circuit.json
bun run export:manufacturing-review
```

The physical geometry gate now passes. Also run shorts, placement and silkscreen checks on the `circuit.json` inside the newly printed review directory. Export success does not grant manufacturing sign-off. Network access is needed for live public supplier-footprint verification; routing itself is local. Current logs use `dist/export-integration-*.log`; older named logs above are historical evidence.