AnasSarkiz/am625sip-linux

validation/failed-underside/build.log

PCB

Schematic

Building 1 file(s)...
Building index.circuit.tsx...
Generating circuit JSON...
Wrote debug artifact: dist/autorouter-debug/placement-unrouted.png
Autorouting <group#462 name=".processor" /> phase 1 start: connections=6, obstacles=431, previous_traces=0 
  connections: TP_SD_CMD.pin1 to U1.A21, TP_SD_D0.pin1 to U1.A22, TP_SD_D1.pin1 to U1.B21, TP_SD_CLK.pin1 to U1.B22, TP_SD_D2.pin1 to U1.C21, TP_SD_D3.pin1 to U1.D22
Wrote debug artifact: dist/autorouter-debug/phase-0.input.simple-route.json
  phase 1 progress: solver_phase=nodeDimensionSubdivisionSolver steps=1 progress=0% iterations_per_second=243 elapsed=3.3s
  phase 1 done: routed_traces=6, jumpers=0, errors=0, elapsed=10.5s
Wrote debug artifact: dist/autorouter-debug/phase-0.output.traces.json
Wrote debug artifact: dist/autorouter-debug/phase-0-routed.png
Wrote debug artifact: dist/autorouter-debug/board.meta.json
Circuit JSON written to dist/index/circuit.json
<trace#2186(from:.TP_SD_CMD > .pin1 to:.U1 > .A21) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#2187(from:.TP_SD_D0 > .pin1 to:.U1 > .A22) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#2188(from:.TP_SD_D1 > .pin1 to:.U1 > .B21) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#2189(from:.TP_SD_CLK > .pin1 to:.U1 > .B22) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#2190(from:.TP_SD_D2 > .pin1 to:.U1 > .C21) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#2191(from:.TP_SD_D3 > .pin1 to:.U1 > .D22) /> is missing a name. Add a name prop to make the trace easier to identify.
No <schematicsheet> was found. Add a <schematicsheet> to define the schematic drawing area.
TP_SD_CMD has no courtyard
TP_SD_D0 has no courtyard
TP_SD_D1 has no courtyard
TP_SD_CLK has no courtyard
TP_SD_D2 has no courtyard
TP_SD_D3 has no courtyard
All pins on U1 are underspecified (no pinAttributes set)
U1 has no pin with requires_power=true
U1 has no pin with requires_ground=true
PCB trace trace[.TP_SD_D2 > port.1, .U1 > port.MMC1_DAT2_C21] is too close to trace[.TP_SD_CMD > port.1, .U1 > port.MMC1_CMD_A21] (gap: 0.079mm)
PCB trace trace[.TP_SD_D2 > port.1, .U1 > port.MMC1_DAT2_C21] overlaps with pcb_smtpad "pcb_port[.U1 > .A21]" (accidental contact)
PCB trace trace[.TP_SD_D2 > port.1, .U1 > port.MMC1_DAT2_C21] overlaps with pcb_smtpad "pcb_port[.U1 > .B21]" (accidental contact)
PCB trace trace[.TP_SD_D1 > port.1, .U1 > port.MMC1_DAT1_B21] overlaps with pcb_smtpad "pcb_port[.U1 > .A20]" (accidental contact)
Pad pcb_port[.U1 > .A23] and trace trace[.TP_SD_CLK > port.1, .U1 > port.MMC1_CLK_B22] are too close (clearance: 0.019mm, minimum: 0.09mm)
Pad pcb_port[.U1 > .A22] and trace trace[.TP_SD_CLK > port.1, .U1 > port.MMC1_CLK_B22] are too close (clearance: 0.063mm, minimum: 0.09mm)
[profile] index.circuit.tsx: 13707.7ms
Generating preview images...
[index] Generating PCB SVG...
[index] Written pcb.svg
[index] Generating PCB PNG...
[index] Written pcb.png

Profile Summary (slowest first)
  13707.7ms index.circuit.tsx

Build complete
  Circuits  1 passed
  Options   pcb-png, pcb-svgs, profile, autorouter-debug, autorouter-timeout, autorouter-dump-srj
  Output    dist

⚠ Build completed with errors
Build exiting with code 0: build finished successfully