AnasSarkiz/am625sip-linux

validation/failed-inner-row/build.log

PCB

Schematic

Building 1 file(s)...
Building stages/02-inner-row-breakout.circuit.tsx...
Generating circuit JSON...
Wrote debug artifact: dist/autorouter-debug/placement-unrouted.png
Autorouting <group#444 name=".processor" /> phase 1 start: connections=3, obstacles=428, previous_traces=0 
  connections: TP_SD_CMD.pin1 to U1.A21, TP_SD_D0.pin1 to U1.A22, TP_SD_D1.pin1 to U1.B21
Wrote debug artifact: dist/autorouter-debug/phase-0.input.simple-route.json
  phase 1 progress: solver_phase=nodeDimensionSubdivisionSolver steps=1 progress=0% iterations_per_second=218 elapsed=3.1s
  phase 1 done: routed_traces=3, jumpers=0, errors=0, elapsed=10.9s
Wrote debug artifact: dist/autorouter-debug/phase-0.output.traces.json
Wrote debug artifact: dist/autorouter-debug/phase-0-routed.png
Solver inputs written to /Users/anassarkiz/Documents/Codex/2026-09-05/a-minimum-practical-ti-am625sip-linux/outputs/am625sip-linux/dist/solver-debug/stages/02-inner-row-breakout/solver-inputs.json
Wrote debug artifact: dist/autorouter-debug/board.meta.json
Circuit JSON written to dist/stages/02-inner-row-breakout/circuit.json
<trace#2159(from:.TP_SD_CMD > .pin1 to:.U1 > .A21) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#2160(from:.TP_SD_D0 > .pin1 to:.U1 > .A22) /> is missing a name. Add a name prop to make the trace easier to identify.
<trace#2161(from:.TP_SD_D1 > .pin1 to:.U1 > .B21) /> is missing a name. Add a name prop to make the trace easier to identify.
No <schematicsheet> was found. Add a <schematicsheet> to define the schematic drawing area.
TP_SD_CMD has no courtyard
TP_SD_D0 has no courtyard
TP_SD_D1 has no courtyard
All pins on U1 are underspecified (no pinAttributes set)
U1 has no pin with requires_power=true
U1 has no pin with requires_ground=true
PCB trace trace[.TP_SD_D1 > port.1, .U1 > port.MMC1_DAT1_B21] overlaps with pcb_smtpad "pcb_port[.U1 > .A21]" (accidental contact)
[profile] stages/02-inner-row-breakout.circuit.tsx: 13503.0ms
Generating preview images...
[stages/02-inner-row-breakout] Generating PCB SVG...
[stages/02-inner-row-breakout] Written pcb.svg
[stages/02-inner-row-breakout] Generating PCB PNG...
[stages/02-inner-row-breakout] Written pcb.png

Profile Summary (slowest first)
  13503.0ms stages/02-inner-row-breakout.circuit.tsx

Build complete
  Circuits  1 passed
  Options   pcb-png, pcb-svgs, profile, autorouter-debug, autorouter-timeout, autorouter-dump-srj, solver-debug
  Output    dist

⚠ Build completed with errors
Build exiting with code 0: build finished successfully