AnasSarkiz/am625sip-linux

README.md

# AM625SiP Linux computer — incremental development

Work in progress. The current default revision contains the AM6254ATLHJAMKR processor and two routed microSD breakout pads (CMD and D0). It cannot boot or be manufactured as a functioning computer.

## Current stage

- Processor placement and two outer-row breakout routes pass netlist, placement, TypeScript and circuit JSON error checks. Native `fanout` creates escape copper and breakout points; the default Pipeline 9 router completes the connections. Both phases join physically.
- Two schematic sheets divide all 425 processor pins into named signal, storage, display, control, power and ground sections. Each ball appears exactly once.
- The board is 160 × 120 mm with a 64 × 64 mm processor subcircuit and a 32 × 32 mm fanout region. The Pipeline 9 route cache is verified. Native fanout is marked `cacheable: false` in this core release and still reruns; full fanout caching is an outstanding tooling requirement.
- The next native-fanout stage adds MMC1_DAT1 on B21. Placement passes, but native fanout can route only 2 of 3 connections. `validation/failed-native-inner-row` contains the real circuit, solver inputs, logs and diagnostics. Independent single-signal buses with all 12 supported exit directions fail on both fanout 0.0.46 and upstream 0.0.57. Larger breakout regions did not resolve the local escape failure. Earlier direct-routing failures remain archived separately.
- Power, decoupling, clocks, reset/straps, debug connectors, microSD socket, USB and HDMI are not yet implemented. They must not be added as completed stages until the processor escape is validated.
- Pin power requirements remain unspecified in this early geometry stage; the build reports these warnings. Netlist success here does not establish electrical completeness.

Run `tsci build index.circuit.tsx --pcb-svgs --pcb-png`, then `node scripts/validate-artifact.mjs 2` and `bun scripts/export-schematic-sheets.mjs`. The explicit error check is mandatory: this CLI version has returned exit code 0 for builds containing routing DRC errors.

## Design requirements

- TSX, tscircuit's default local autorouter, explicitly `beta_pipeline9` for global routing. Use native `fanout` for the BGA escape phase.
- Processor with integrated 512 MB LPDDR4; microSD boot and root filesystem.
- Sequenced power, local decoupling, clocks, reset, boot straps, UART and JTAG.
- USB connectivity and an external DPI-to-HDMI bridge and HDMI connector.
- Current board: 160 × 120 mm; enlarge when placement requires it.
- Real subcircuits. The CLI supplies a persistent `.tscircuit/cache` engine. Verify actual routing-cache hits after routed stages.
- Check netlist, check placement, run the real circuit, refresh SVG, then `tsci push` each successful stage.

## Sources

- [TI AM625SiP datasheet SPRSP98A](https://www.ti.com/lit/gpn/am625sip): Figure 5-1, Table 5-1, package AMK0425A. All 425 populated balls are modeled, including reassigned DDR balls. Land diameter 0.30 mm, pitch 0.50 mm, body 13 × 13 mm.
- [TI SiP escape-routing guide SPRADD4](https://www.ti.com/lit/an/spradd4/spradd4.pdf): via channels and four-layer reference stackup.
- [TI SiP PMIC application note SLVAFP8](https://www.ti.com/lit/pdf/slvafp8): TPS6521902/08 configurations and sequencing.
- [TI SK-AM62-SIP design reference](https://www.ti.com/tool/SK-AM62-SIP): HDMI bridge, storage and connectivity reference.

The related AM625 ALW footprint imported from JLCPCB C6120421 was used only to cross-check populated ball positions. It is not used as the SiP part, and its supplier code and 3D model are not assigned to the SiP. SiP signal names and land size follow TI's SiP datasheet.

## Validation scope

A successful software build is not a Linux boot test. Electrical completeness, power integrity, high-speed interface impedance/skew, thermal performance and physical bring-up must be validated before manufacturing.

## Routing blocker and next work

The B21 local escape needs a via in an unpopulated lattice position. A diagnostic geometry audit finds zero legal adjacent half-pitch sites, while the empty C22 position has 0.1214 mm via-to-pad edge clearance and 0.1586 mm escape-stub clearance against the complete 425-pad footprint, both above the 0.09 mm rule. This is local geometry evidence, not a completed route. No diagnostic copper has been inserted into the circuit.

The fanout solver needs general sparse-BGA escape support and a regression for this input before the inner-row stage can pass. The current [upstream via-site matcher](https://github.com/tscircuit/fanout-solver/blob/b859939b04910965ac109c07e1dda6d2d4f250d5/lib/match-component-dogbone-via-sites.ts) enumerates adjacent interstitial positions. Preserve the complete pad obstacles and manufacturing rules when fixing the solver; rerun the native three-signal stage, then the six-signal stage, before integrating later component groups.

Sheet SVGs are `dist/index/schematic-processor.svg`, `dist/index/schematic-processor_power.svg`, and `dist/index/schematic-all-sheets.svg`. They are generated from the actual Circuit JSON with the official schematic renderer.