AnasSarkiz/NEMA14_RP2040

src/layer-routing-policy.json

{
  "inner1_allowed_nets": [
    "A_MINUS",
    "A_PLUS",
    "BOOT_PAD",
    "BUZZER_GATE",
    "BUZZER_PWM",
    "B_MINUS",
    "B_PLUS",
    "DATA_CC1",
    "DATA_CC2",
    "DATA_PRESENT",
    "DATA_VBUS",
    "DCK",
    "DIO",
    "DIR",
    "ENABLE_N",
    "GND",
    "LED_B",
    "LED_G",
    "LED_R",
    "PD_CC1",
    "PD_CC2",
    "PD_GOOD",
    "PWR_LED_A",
    "QSPI_SCLK",
    "QSPI_SD0",
    "QSPI_SD1",
    "QSPI_SD2",
    "QSPI_SD3",
    "QSPI_SS",
    "RUN",
    "SLEEP",
    "STATUS_B_C",
    "STATUS_B_K",
    "STATUS_G_C",
    "STATUS_G_K",
    "STATUS_R_C",
    "STATUS_R_K",
    "STEP",
    "SWCLK",
    "SWDIO",
    "TEMP_SCL",
    "TEMP_SDA",
    "V1V1",
    "V3V3",
    "VM_SENSE",
    "XIN",
    "XOUT",
    "XTAL_OUT"
  ],
  "maximum_inner1_trace_section_length_mm": 30,
  "maximum_clock_or_flash_inner1_section_mm": 15,
  "maximum_A_MINUS_inner1_section_mm": 8,
  "minimum_A_MINUS_inner1_width_mm": 0.3,
  "USB_inner_signal_tracks_allowed": false,
  "required_main_inner1_ground_region_area_mm2": 700,
  "rationale": "Inner1 retains grounded fill with bounded control routes and short motor-pin transitions totaling no more than 8 mm per phase. Motor trunks use outer/inner2 copper. Every phase transition is at least 0.30 mm wide and must pass full-budget thermal, physical connectivity, clearance, ground-plane area and USB reference checks.",
  "maximum_total_phase_inner1_length_mm": 8,
  "minimum_phase_inner1_width_mm": 0.3,
  "USB_construction_reference_buffer_mm": 0.4,
  "USB_reference_requires_full_track_width": true,
  "USB_construction_reference_rationale": "Pair outer edge is 0.330 mm from the centreline. A 0.400 mm construction buffer plus the existing 0.15 mm copper clearance and 0.02 mm grid margin leaves 0.04 mm beyond the 0.20 mm ground-fill setback. Final exact full-track ground-reference geometry remains mandatory."
}