AnasSarkiz/NEMA14_RP2040

A NEMA motor assembly concept with a controller board, four proposed M3 screws and spacers, motor lead splices, and a JST 4-pin connector harness.

Version
1.13.0
License
ISC
Stars
0

artifacts/same-side-pruned-stubs.json

PCBPCB preview for artifacts/same-side-pruned-stubs.json
SchematicSchematic preview for artifacts/same-side-pruned-stubs.json
[
  {
    "removed_trace_ids": [
      "freerouted_trace_166",
      "same_side_retained_freerouted_trace_365",
      "same_side_retained_freerouted_trace_396"
    ],
    "retained_live_traces": [
      "same_side_retained_freerouted_trace_370"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "freerouted_trace_116"
    ],
    "retained_live_traces": [],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "jst_baseline_STEP_segment_3",
      "jst_baseline_STEP_segment_6"
    ],
    "retained_live_traces": [
      "freerouted_trace_32",
      "jst_baseline_STEP_segment_1",
      "same_side_repair_2_STEP_0"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
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      "freerouted_trace_277",
      "freerouted_trace_304",
      "freerouted_trace_342",
      "freerouted_trace_386",
      "same_side_retained_feedback_retained_same_side_repair_0_STEP_0",
      "same_side_retained_feedback_retained_same_side_repair_2_STEP_0_rerouted",
      "same_side_retained_feedback_retained_same_side_retained_same_side_retained_freerouted_trace_377"
    ],
    "retained_live_traces": [],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [],
    "retained_live_traces": [],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "freerouted_trace_237",
      "freerouted_trace_239",
      "same_side_repair_43_STATUS_R_C_1"
    ],
    "retained_live_traces": [
      "same_side_repair_6_MCU_DP_3"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "feedback_fanout_pcb_port_152",
      "freerouted_trace_109",
      "inner1_local_escape_DIR_0",
      "inner1_local_escape_QSPI_SD1_1",
      "inner1_local_escape_QSPI_SD1_1_next",
      "inner1_local_escape_QSPI_SD1_1_next_next",
      "inner1_local_escape_QSPI_SD1_1_next_next_next",
      "inner1_local_escape_QSPI_SD3_1",
      "inner1_local_escape_QSPI_SD3_1_next",
      "inner1_local_escape_V3V3_0",
      "inner1_local_escape_V3V3_0_next",
      "same_side_repair_23_PWR_LED_A_0",
      "same_side_repair_29_QSPI_SCLK_1_layer_section_0",
      "same_side_repair_39_PWR_LED_A_1_layer_section_0",
      "same_side_repair_3_SWCLK_3",
      "same_side_repair_4_MCU_DP_1",
      "same_side_repair_4_SWCLK_4"
    ],
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      "same_side_repair_42_STATUS_R_C_0",
      "same_side_repair_6_SWCLK_6"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "same_side_repair_23_SLEEP_0_layer_section_0",
      "same_side_repair_2_SWCLK_2"
    ],
    "retained_live_traces": [
      "same_side_repair_6_SWCLK_6"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "same_side_repair_1_DATA_VBUS_0",
      "same_side_repair_1_SWCLK_1",
      "same_side_repair_2_DATA_VBUS_1_layer_section_0"
    ],
    "retained_live_traces": [],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [],
    "retained_live_traces": [
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      "same_side_repair_3_VM_SENSE_0"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
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      "inner1_local_escape_DIR_0_next",
      "same_side_repair_0_GND_0_layer_section_1",
      "same_side_repair_0_RUN_0_layer_section_1",
      "same_side_repair_11_SWDIO_0_layer_section_0",
      "same_side_repair_13_QSPI_SD2_1",
      "same_side_repair_15_BUCK_SW_0_layer_section_1",
      "same_side_repair_1_B_PLUS_0_layer_section_1",
      "same_side_repair_1_B_PLUS_0_layer_section_2",
      "same_side_repair_2_STATUS_B_K_0"
    ],
    "retained_live_traces": [
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      "same_side_repair_14_SWDIO_0",
      "same_side_repair_2_V1V1_0_layer_section_1",
      "same_side_repair_2_V3V3_0_rerouted_rerouted",
      "same_side_repair_5_V3V3_0"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "same_side_repair_1_RUN_1_layer_section_0",
      "same_side_repair_6_XTAL_OUT_2"
    ],
    "retained_live_traces": [
      "same_side_repair_10_V1V1_0"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "same_side_repair_9_XTAL_OUT_2"
    ],
    "retained_live_traces": [],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "review_baseline_freerouted_trace_319_run_1",
      "review_baseline_same_side_repair_0_VM_SENSE_0_run_0",
      "review_baseline_same_side_repair_2_V1V1_2_run_0",
      "review_baseline_same_side_repair_6_SWCLK_6_run_0"
    ],
    "retained_live_traces": [
      "review_baseline_freerouted_trace_435_run_0",
      "review_baseline_same_side_repair_0_VM_SENSE_0_run_1",
      "review_baseline_same_side_repair_34_V3V3_11_run_0",
      "review_baseline_same_side_repair_3_VM_SENSE_0_run_0",
      "same_side_repair_0_QSPI_SCLK_0"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "review_baseline_same_side_repair_1_ENABLE_N_0_run_0",
      "review_baseline_same_side_repair_5_SWCLK_5_run_0"
    ],
    "retained_live_traces": [
      "review_baseline_same_side_repair_34_V3V3_11_run_0"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [],
    "retained_live_traces": [
      "review_baseline_same_side_repair_34_V3V3_11_run_0"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
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      "review_baseline_review_baseline_freerouted_trace_319_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_freerouted_trace_325_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_freerouted_trace_329_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_freerouted_trace_41_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_freerouted_trace_422_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_freerouted_trace_434_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_freerouted_trace_443_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_freerouted_trace_445_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_freerouted_trace_5_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_freerouted_trace_68_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_freerouted_trace_74_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_inner1_local_escape_V3V3_0_next_next_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_0_LED_B_0_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_0_QSPI_SCLK_0_layer_section_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_0_QSPI_SCLK_0_layer_section_1_run_0_run_1_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_0_VM_SENSE_0_run_1_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_10_DATA_PRESENT_1_layer_section_0_run_0_run_1_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_12_SWDIO_0_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_13_STATUS_R_C_0_layer_section_2_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_13_SWDIO_2_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_16_V3V3_4_layer_section_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_1_DIR_0_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_1_DIR_0_run_0_run_1_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_1_V1V1_1_layer_section_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_23_A_MINUS_0_layer_section_4_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_24_STATUS_R_K_0_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_26_STATUS_R_K_2_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_26_STATUS_R_K_2_run_0_run_1_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_27_QSPI_SS_2_layer_section_0_run_0_run_1_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_27_STATUS_R_K_3_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_27_V3V3_4_layer_section_0_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_2_DATA_VBUS_0_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_2_DATA_VBUS_1_layer_section_2_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_2_DATA_VBUS_1_layer_section_3_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_2_DATA_VBUS_1_layer_section_3_run_0_run_1_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_2_DIR_0_layer_section_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_2_V1V1_0_layer_section_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_2_V3V3_0_rerouted_rerouted_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_34_V3V3_11_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_39_PWR_LED_A_1_layer_section_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_3_PWR_LED_A_2_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_4_LED_R_0_layer_section_2_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_5_V3V3_0_rerouted_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_7_DATA_VBUS_2_layer_section_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_8_PD_VBUS_4_layer_section_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_9_SLEEP_0_layer_section_0_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_9_SLEEP_0_layer_section_2_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_9_SLEEP_0_layer_section_7_run_0_run_1_via_clearance_run_0",
      "review_baseline_same_side_repair_14_STATUS_R_C_0_layer_section_0_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_2_VM_SENSE_0_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_3_BOOT_PAD_0_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_4_STATUS_B_C_3_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_5_LED_R_0_layer_section_1_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_6_LED_B_0_run_1_via_clearance_run_0",
      "review_baseline_same_side_repair_6_LED_B_0_run_2_via_clearance_run_0",
      "review_baseline_same_side_repair_7_DATA_VBUS_1_layer_section_1_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_8_DATA_CC1_0_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_9_ENABLE_N_0_layer_section_0_run_0_via_clearance_run_0",
      "review_escape_Q_STATUS_B_pin2",
      "review_escape_R_CC2_pin1",
      "review_escape_R_USB_SENSE_H_pin2",
      "review_escape_R_USB_SENSE_L_pin1",
      "review_escape_TP_SWDIO_pin1",
      "review_escape_U_ENCODER_SCL",
      "review_escape_U_FLASH_CLK",
      "review_escape_U_PD_CC2",
      "reviewed_local_U_ENCODER_SCL",
      "reviewed_local_U_MCU_GPIO8",
      "reviewed_local_U_MCU_QSPI_SD0",
      "reviewed_local_critical_review_baseline_freerouted_trace_351_run_0",
      "same_side_repair_0_QSPI_SCLK_0",
      "same_side_repair_12_SLEEP_1",
      "same_side_repair_16_STATUS_B_C_0_layer_section_0",
      "same_side_repair_18_B_PLUS_0",
      "same_side_repair_25_STEP_0",
      "same_side_repair_26_STEP_1_layer_section_0",
      "same_side_repair_2_SWDIO_0",
      "same_side_repair_31_STATUS_G_C_0_layer_section_3",
      "same_side_repair_7_LED_B_0",
      "same_side_repair_82_STATUS_G_C_0_layer_section_1"
    ],
    "retained_live_traces": [
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      "review_baseline_review_baseline_freerouted_trace_314_run_0_run_0_via_clearance_run_0",
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      "review_baseline_review_baseline_same_side_repair_0_V1V1_0_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_0_V3V3_0_layer_section_0_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_1_TEMP_SCL_0_run_0_run_1_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_1_VM_SENSE_0_layer_section_5_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_34_QSPI_SD3_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_5_V3V3_3_layer_section_2_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_7_PD_VBUS_3_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_8_DATA_VBUS_3_layer_section_3_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_9_SLEEP_0_layer_section_3_run_0_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_1_VM_SENSE_1_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_3_V3V3_1_run_0_via_clearance_run_0",
      "same_side_repair_11_VM_SENSE_1",
      "same_side_repair_29_VM_SENSE_4_layer_section_1"
    ],
    "live_pad_connectivity_unchanged": true
  },
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      "review_baseline_review_baseline_same_side_repair_23_A_MINUS_0_layer_section_7_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_2_PWR_LED_A_1_layer_section_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_8_STATUS_B_K_0_layer_section_1_run_0_run_1_via_clearance_run_0",
      "review_baseline_same_side_repair_12_V1V1_1_layer_section_0_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_14_STATUS_R_C_0_layer_section_1_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_7_DATA_VBUS_1_layer_section_0_run_0_via_clearance_run_0",
      "reviewed_local_C_IO22_pin1",
      "reviewed_local_U_MCU_QSPI_SD0",
      "same_side_repair_0_ENABLE_N_0",
      "same_side_repair_0_QSPI_SD2_0_layer_section_0",
      "same_side_repair_10_DATA_CC2_0_layer_section_1",
      "same_side_repair_17_SLEEP_0_rerouted",
      "same_side_repair_1_LED_B_1",
      "same_side_repair_1_QSPI_SD2_0",
      "same_side_repair_20_V3V3_6",
      "same_side_repair_31_STATUS_G_C_0_layer_section_2",
      "same_side_repair_3_LED_B_0",
      "same_side_repair_4_RUN_0_layer_section_1",
      "same_side_repair_5_SWDIO_0_layer_section_1",
      "same_side_repair_62_DATA_VBUS_8_layer_section_1",
      "same_side_repair_77_STATUS_R_K_1_layer_section_1",
      "same_side_repair_7_A_MINUS_1",
      "same_side_repair_8_LED_B_1"
    ],
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      "review_baseline_review_baseline_same_side_repair_6_V3V3_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_review_baseline_same_side_repair_8_STATUS_B_K_0_layer_section_1_run_0_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_0_DATA_CC2_0_layer_section_2_run_0_via_clearance_run_0",
      "same_side_repair_0_USB_DP_0_layer_section_1",
      "same_side_repair_10_DATA_CC2_0_layer_section_0",
      "same_side_repair_19_SLEEP_2_layer_section_2",
      "same_side_repair_28_DIR_1_layer_section_1",
      "same_side_repair_9_DATA_CC1_0_layer_section_0"
    ],
    "live_pad_connectivity_unchanged": true
  },
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      "review_baseline_review_baseline_same_side_repair_5_V3V3_3_layer_section_2_run_0_run_0_via_clearance_run_0",
      "review_baseline_same_side_repair_1_LED_R_0_layer_section_0_run_0_via_clearance_run_0",
      "same_side_repair_0_DATA_CC1_0_layer_section_0",
      "same_side_repair_19_BUZZER_PWM_0_layer_section_0",
      "same_side_repair_59_DIR_0_layer_section_2",
      "same_side_repair_5_RUN_1_layer_section_2",
      "same_side_repair_9_RUN_0_layer_section_0",
      "same_side_repair_9_V3V3_1"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "reviewed_local_Q_STATUS_R_pin3",
      "reviewed_local_U_PD_CC1",
      "reviewed_local_U_PD_PG",
      "same_side_repair_0_BUZZER_PWM_0_layer_section_5",
      "same_side_repair_0_PD_CC1_0_layer_section_0",
      "same_side_repair_0_SLEEP_0_rerouted_rerouted_rerouted_rerouted_layer_section_1",
      "same_side_repair_1_TEMP_SDA_1_layer_section_0",
      "usb_cc_escape_J_DATA_CC1",
      "usb_cc_escape_J_PD_CC2"
    ],
    "retained_live_traces": [
      "review_baseline_review_baseline_freerouted_trace_180_run_0_run_0_via_clearance_run_0",
      "reviewed_local_J_DATA_CC1",
      "reviewed_local_U_MCU_GPIO29",
      "reviewed_local_U_MCU_QSPI_SD2",
      "same_side_repair_0_LED_B_0_layer_section_3"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "reviewed_local_R_BUZZER_GATE_pin1",
      "same_side_repair_0_STATUS_B_C_0_layer_section_0"
    ],
    "retained_live_traces": [
      "review_baseline_review_baseline_freerouted_trace_180_run_0_run_0_via_clearance_run_0",
      "reviewed_local_R_TEMP_SDA_pin1",
      "same_side_repair_0_DATA_CC2_0_rerouted_rerouted_layer_section_0",
      "same_side_repair_0_RUN_0_layer_section_1",
      "same_side_repair_0_SLEEP_0"
    ],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [
      "reviewed_local_U_MCU_GPIO2",
      "reviewed_local_U_MCU_GPIO29",
      "reviewed_local_critical_review_baseline_same_side_repair_14_BUCK_BST_0_layer_section_0_run_0",
      "same_side_repair_0_LED_G_0_rerouted_layer_section_1",
      "same_side_repair_39_STATUS_B_C_0_layer_section_0"
    ],
    "retained_live_traces": [],
    "live_pad_connectivity_unchanged": true
  },
  {
    "removed_trace_ids": [],
    "retained_live_traces": [
      "same_side_repair_0_LED_G_0_rerouted_layer_section_2"
    ],
    "live_pad_connectivity_unchanged": true
  }
]