0hmX/am62l-lpddr4-ti-pth-router

This code defines a hardware-oriented React/TypeScript setup for a PCB breakout circuit featuring an AM62L LPDDR4 interface, including detailed PCB component placement, routing algorithms, and validation scripts for DDR connections, via placement, and manufacturing constraints.

Version
1.0.1
License
unset
Stars
0

scripts/verify-ddr-byte1-layers.ts

type RoutePoint = {
  route_type: string
  layer?: string
}

type FanoutTrace = {
  connection_name: string
  route: RoutePoint[]
}

type FanoutInput = {
  buses: Array<{
    busId: string
    preferredLayers?: string[]
  }>
  connections: Array<{
    name: string
    source_trace_id: string
  }>
}

export {}

const debugDirectory = process.argv[2] ?? "dist/autorouter-debug"

const loadPhase = async (phaseIndex: number) => {
  const input = (await Bun.file(
    `${debugDirectory}/phase-${phaseIndex}.input.simple-route.json`,
  ).json()) as FanoutInput
  const traces = (await Bun.file(
    `${debugDirectory}/phase-${phaseIndex}.output.traces.json`,
  ).json()) as FanoutTrace[]
  const sourceTraceIdByConnectionName = new Map(
    input.connections.map((connection) => [
      connection.name,
      connection.source_trace_id,
    ]),
  )

  const exitLayerBySourceTraceId = new Map<string, string>()
  for (const trace of traces) {
    const sourceTraceId = sourceTraceIdByConnectionName.get(
      trace.connection_name,
    )
    if (!sourceTraceId) continue
    const exitLayer = [...trace.route]
      .reverse()
      .find((routePoint) => routePoint.route_type === "wire")?.layer
    if (!exitLayer) {
      throw new Error(`No fanout exit layer found for ${sourceTraceId}`)
    }
    exitLayerBySourceTraceId.set(sourceTraceId, exitLayer)
  }

  return { input, exitLayerBySourceTraceId }
}

const soc = await loadPhase(0)
const ram = await loadPhase(1)

if (soc.exitLayerBySourceTraceId.size !== 33) {
  throw new Error(
    `Expected 33 SoC fanout traces, got ${soc.exitLayerBySourceTraceId.size}`,
  )
}
if (ram.exitLayerBySourceTraceId.size !== 33) {
  throw new Error(
    `Expected 33 RAM fanout traces, got ${ram.exitLayerBySourceTraceId.size}`,
  )
}

const preferredLayersByBusName = new Map(
  soc.input.buses.map((bus) => [bus.busId, bus.preferredLayers]),
)
for (const bus of ram.input.buses) {
  const socPreferredLayers = preferredLayersByBusName.get(bus.busId)
  if (
    !socPreferredLayers ||
    JSON.stringify(bus.preferredLayers) !== JSON.stringify(socPreferredLayers)
  ) {
    throw new Error(
      `Mismatched preferredLayers for ${bus.busId}: SoC=${socPreferredLayers?.join(",")}, RAM=${bus.preferredLayers?.join(",")}`,
    )
  }
}

const layerAssignments = [...soc.exitLayerBySourceTraceId].map(
  ([sourceTraceId, socLayer]) => {
    const ramLayer = ram.exitLayerBySourceTraceId.get(sourceTraceId)
    if (!ramLayer) {
      throw new Error(`RAM fanout is missing ${sourceTraceId}`)
    }
    if (socLayer !== ramLayer) {
      throw new Error(
        `Fanout layer mismatch for ${sourceTraceId}: SoC=${socLayer}, RAM=${ramLayer}`,
      )
    }
    return { sourceTraceId, layer: socLayer }
  },
)

console.log(JSON.stringify({ layerAssignments }, null, 2))