0hmX/am62l-lpddr4-ti-pth-router

am62l-lpddr4-breakout-circuit.tsx

import { ballMap } from "@tsci/0hmX.mt53e1g16d1zw-footprint"
import { Fragment } from "react"
import type { Am62lFanoutAlgorithmFn } from "./autorouting/am62l-free-space-fanout"
import type { Am62lMiddleChannelAlgorithmFn } from "./autorouting/am62l-middle-channel"
import { AM62L32_TI_LAND } from "./components/am62l32-ti-land"
import { MT53E1G16D1ZW_NSMD } from "./components/mt53e1g16d1zw-nsmd"
import {
  DDR_ADDR_CTRL_TRACE_NAMES,
  DDR_BYTE0_TRACE_NAMES,
  DDR_BYTE1_TRACE_NAMES,
  DDR_CONNECTIONS,
  DDR_SOC_PHYSICAL_PINS,
} from "./ddr-connections"

const usedSocPins = new Set<number>(DDR_SOC_PHYSICAL_PINS)
const socNoConnect = Array.from({ length: 373 }, (_, index) => index + 1)
  .filter((pin) => !usedSocPins.has(pin))
  .map((pin) => `pin${pin}`)

const usedMemorySignals = new Set(
  DDR_CONNECTIONS.map(({ memorySignal }) => memorySignal),
)
const memoryNoConnect = ballMap
  .map(({ signal }, index) => ({ signal, selector: `pin${index + 1}` }))
  .filter(({ signal }) => !usedMemorySignals.has(signal))
  .map(({ selector }) => selector)

const SIGNAL_LAYERS = [
  "top",
  "inner1",
  "inner2",
  "inner3",
  "inner4",
  "inner5",
  "inner6",
  "bottom",
] as const

export type Am62lLpddr4BreakoutCircuitProps = {
  socFanoutAlgorithm?: Am62lFanoutAlgorithmFn
  ramFanoutAlgorithm?: Am62lFanoutAlgorithmFn
  middleChannelAlgorithm?: Am62lMiddleChannelAlgorithmFn
}

export const Am62lLpddr4BreakoutCircuit = ({
  socFanoutAlgorithm,
  ramFanoutAlgorithm,
  middleChannelAlgorithm,
}: Am62lLpddr4BreakoutCircuitProps = {}) => {
  const socFanoutAutorouter = socFanoutAlgorithm
    ? {
        local: true,
        groupMode: "subcircuit" as const,
        preset: "fanout" as const,
        algorithmFn: socFanoutAlgorithm,
      }
    : ("fanout" as const)
  const ramFanoutAutorouter = ramFanoutAlgorithm
    ? {
        local: true,
        groupMode: "subcircuit" as const,
        preset: "fanout" as const,
        algorithmFn: ramFanoutAlgorithm,
      }
    : ("fanout" as const)

  return (
    <board
      name="AM62L_LPDDR4_BREAKOUT_REPRO"
      width="90mm"
      height="25mm"
      layers={8}
      defaultTraceWidth="0.08128mm"
      minTraceWidth="0.08128mm"
      minTraceToPadEdgeClearance="0.08128mm"
      minViaEdgeToPadEdgeClearance="0.08128mm"
      minViaHoleEdgeToViaHoleEdgeClearance="0.1016mm"
      minViaHoleDiameter="0.2032mm"
      minViaPadDiameter="0.4572mm"
      pcbStyle={{ viaHoleDiameter: "0.2032mm", viaPadDiameter: "0.4572mm" }}
      autorouterEffortLevel="10x"
      autorouter={
        middleChannelAlgorithm
          ? {
              local: true,
              groupMode: "subcircuit",
              algorithmFn: middleChannelAlgorithm,
            }
          : undefined
      }
    >
      <breakout
        name="SOC_BREAKOUT"
        pcbX={-20}
        pcbY={0}
        fanoutBoundaryPadding={{
          top: "5mm",
          right: "22.5mm",
          bottom: "5mm",
          left: "1mm",
        }}
        paddingTop="5mm"
        paddingRight="22.5mm"
        paddingBottom="5mm"
        paddingLeft="1mm"
        fanoutRoutingLayers={[...SIGNAL_LAYERS]}
        busFanoutDirections={{
          DDR_BYTE1: "top_right",
          DDR_ADDR_CTRL: "center_right",
          DDR_BYTE0: "bottom_right",
        }}
        autorouter={socFanoutAutorouter}
      >
        <AM62L32_TI_LAND
          name="U1"
          pcbX={0}
          pcbY={0}
          pcbRotation={180}
          noSchematicRepresentation
          noConnect={socNoConnect as any}
        />
      </breakout>

      <breakout
        name="RAM_BREAKOUT"
        pcbX={20.116917}
        pcbY={-0.050917}
        fanoutBoundaryPadding={{
          top: "5mm",
          right: "1mm",
          bottom: "5mm",
          left: "22.5mm",
        }}
        paddingTop="5mm"
        paddingRight="1mm"
        paddingBottom="5mm"
        paddingLeft="22.5mm"
        fanoutRoutingLayers={[...SIGNAL_LAYERS]}
        busFanoutDirections={{
          DDR_BYTE1: "top_left",
          DDR_ADDR_CTRL: "center_left",
          DDR_BYTE0: "bottom_left",
        }}
        autorouter={ramFanoutAutorouter}
      >
        <MT53E1G16D1ZW_NSMD
          name="U2"
          pcbX={0}
          pcbY={0}
          pcbRotation={90}
          noSchematicRepresentation
          noConnect={memoryNoConnect as any}
        />
      </breakout>

      <bus
        name="DDR_BYTE0"
        connections={DDR_BYTE0_TRACE_NAMES}
        preferredLayers={[
          "inner2",
          "inner3",
          "inner4",
          "inner5",
          "inner6",
          "bottom",
          "inner1",
        ]}
      />
      <bus
        name="DDR_BYTE1"
        connections={DDR_BYTE1_TRACE_NAMES}
        preferredLayers={[
          "inner4",
          "inner5",
          "inner6",
          "bottom",
          "inner1",
          "inner2",
          "inner3",
        ]}
      />
      <bus
        name="DDR_ADDR_CTRL"
        connections={DDR_ADDR_CTRL_TRACE_NAMES}
        preferredLayers={[
          "bottom",
          "inner1",
          "inner2",
          "inner3",
          "inner4",
          "inner5",
          "inner6",
        ]}
      />

      {/* Differential-pair declarations are temporarily disabled because Core
          PR #3304 expands their connectivity keys into multiple breakout-local
          SRJ connections. All 33 signals route independently. Bus declaration
          order is preserved so former pair members retain adjacent coordinated
          breakout targets where the upstream winding solver permits. */}
      {DDR_CONNECTIONS.map(({ socSignal, memorySignal, traceName }) => (
        <Fragment key={traceName}>
          <trace
            name={traceName}
            from={`U1.${socSignal}`}
            to={`U2.${memorySignal}`}
          />
        </Fragment>
      ))}
    </board>
  )
}