0hmX/am62l-lpddr4-ti-pth-router

ROUTING_PROMPT.md

# Prompt: route the AM62L and LPDDR4 breakouts

> Current implementation override: disable the DQS0, DQS1, and CK0
> `<differentialpair>` declarations and route all 33 signals independently.
> Preserve their existing bus order so the upstream coordinated breakout solver
> can keep former pair members adjacent where possible. Do not implement
> differential-pair coupling or validation in the custom fanout solver.

Work only in
`/Users/ankan/Documents/tscircuits/worktrees/am62l-custom-router-prefactor/am62l-lpddr4-breakout-repro`.
Do not use sub-agents.

Implement and wire a project-local custom fanout autorouter for both
`SOC_BREAKOUT` and `RAM_BREAKOUT`. The project is already pinned to the built
head of tscircuit/core PR #3304 (`646a2658a3c3a539e05146a0c9fa468513cbce33`),
which supplies the coordinated winding breakout-point solver. Keep that Core
behavior responsible for choosing the shared breakout points and target layers;
the new algorithm is responsible for routing actual copper from every BGA ball
to its assigned breakout point.

Use the free-space AM62L router at <https://0hmx.com/> as the geometric
reference. Port its useful ideas into typed TypeScript under `autorouting/`:

1. Build the real pad topology from each incoming `SimpleRouteJson` rather than
   copying the website's fixture arrays.
2. Find connected free-space regions that can legally hold at least two vias.
3. Number pads/connections by distance from those regions.
4. Place independent early-drop vias for sources that can reach free space.
5. Route residual top-layer dogbones toward the permitted breakout side and
   construct ordered 2–3-via strings for them.
6. Route every connection on its prescribed inner layer to its exact Core
   breakout point.
7. Validate all reconstructed geometry before reporting success.

Start at `autorouting/am62l-free-space-fanout.ts` and use
`createAm62lFreeSpaceFanoutAlgorithm`. Put the pure SRJ-to-SRJ solver in a new
module and wire separate algorithm instances through the existing
`socFanoutAlgorithm` and `ramFanoutAlgorithm` props in
`am62l-lpddr4-breakout-circuit.tsx`. Keep `preset: "fanout"`; Core uses the
solver's `getOutputSimpleRouteJson()` result to synchronize the moved fanout
exits with the parent/global connections.

Requirements:

- Derive ball centers, pad geometry, routing bounds, bus membership,
  differential pairs, clearances, trace width, via dimensions, allowed layers,
  exit side, and exact target points from the incoming SRJ. Do not hardcode the
  website's connection IDs, absolute coordinates, `targetGate.x = 9.4`, missing
  pad list, or SoC-only orientation.
- Mirror/rotate the method from actual geometry so the SoC escapes right and
  the RAM escapes left while respecting each bus direction from the circuit.
- Preserve `source_trace_id`, connection names, point IDs, and Core's selected
  layer for every connection. `DDR_BYTE0`, `DDR_BYTE1`, and `DDR_ADDR_CTRL`
  must remain atomic and ordered. Keep DQS0, DQS1, and CK0 differential-pair
  members on the same selected layer and preserve their order.
- Return legal `SimplifiedPcbTrace` wire/via routes and a transformed
  `SimpleRouteJson` whose downstream connection endpoint is exactly the assigned
  breakout point. Preserve supplied traces and metadata needed by later phases.
- Use only straight or 45-degree copper. Enforce trace-to-pad, trace-to-trace,
  trace-to-via, via-to-pad, and via-to-via clearance using the actual SRJ rules.
  Never place a via on a BGA pad.
- Do not add manual `<pcbtrace>`, `<via>`, route-coordinate tables, or fixture-
  specific successful output. Do not silently fall back to the built-in router,
  drop a connection, return a partial solve as successful, or swallow an
  invariant failure. Throw a precise error with the phase, connection, and
  violated constraint.
- Emit progress using the eight phase names already defined in
  `AM62L_FREE_SPACE_FANOUT_PHASES`.

Work incrementally: capture and inspect the actual fanout SRJ, route one focused
bus, then all 33 SoC fanouts, then all 33 RAM fanouts, and finally enable both
custom algorithms in the full board. Keep the board-level global autorouter
separate from these local fanout algorithms.

Before finishing, run:

```sh
bun run typecheck
bun run test:prefactor
bunx tsci check netlist
bunx tsci check schematic-placement
bunx tsci check placement
bunx tsci build index.circuit.tsx --pcb-png \
  --autorouter-debug --autorouter-debug-dir dist/autorouter-debug \
  --autorouter-dump-srj all
bunx tsci check shorts dist/index/circuit.json
```

Inspect the PCB PNG and every cumulative autorouter phase image. Add focused
solver tests for both right-escape and left-escape geometry, all 33 connections,
exact endpoint/layer preservation, bus ordering, differential pairs, and every
clearance class. Finish only when both breakouts and the full board route with
no missing traces, no shorts, and no actionable placement or clearance errors.