0hmX/am62l-lpddr4-ti-pth-router

RESULTS.md

# Routing results

## Custom Core + project-local routers — 2026-08-22

- `tscircuit`: `0.0.2358`
- local `@tscircuit/core`: `0.0.1717`, PR #3304 base
  `646a2658a3c3a539e05146a0c9fa468513cbce33`, plus focused local fixes that
  preserve `algorithmFn` in the fanout preset and propagate coordinated layers
  into parent SRJ endpoints
- SoC fanout: project-local 0hmx-derived free-space algorithm, 33/33 routed
- RAM fanout: the same mirrored geometry algorithm, 33/33 routed
- Middle channel: separate project-local same-layer ordered router, 33/33 routed
- Total PCB traces: 99
- Fanout vias: 66 exact full-stack PTHs, each using TI's
  0.4572/0.2032 mm pad/hole geometry and `top`→`bottom` span
- Breakout trace/space: 0.08128/0.08128 mm minimum
- AM62L lands: 373 at 0.254 mm copper / 0.3048 mm mask opening
- LPDDR4 lands: 200 at 0.32 mm copper / 0.40 mm mask opening
- Board width: 90 mm; U1/U2 X separation: 40.116917 mm (previously
  20.116917 mm)
- Expanded SoC/RAM routing bounds: `[-37.377, -2.623]` mm and
  `[1.381917, 38.851917]` mm, giving a 4.004917 mm middle gap
- Differential-pair declarations: temporarily disabled; all 33 signals route
  independently while their original bus ordering remains intact

### Verification

- TypeScript: passed
- Project solver tests: 7 passed / 41,695 assertions, including fresh actual
  33-net right-escape and left-escape SRJs, exact via spans/dimensions,
  no-via-in-pad clearance, 45-degree turn validation, and package-land geometry
- Netlist: 0 errors, 0 warnings
- Schematic placement: passed
- PCB placement: 0 errors, 0 warnings
- Autorouting phases: 33 + 33 + 33 traces, 0 errors
- Fresh `--autorouter-debug` full build: passed in 27.7 seconds
- Circuit JSON routing/clearance errors: 0
- Measured minimum fanout via-to-BGA-land edge clearance: 0.095094 mm
  (required 0.08128 mm); minimum via-to-via copper-edge clearance: 0.08128 mm
- Copper shorts: none detected

The result remains a routing reproduction, not a production DDR design; the
electrical/manufacturing omissions in the README still apply.

## Before — registry release 1.0.7

- `tscircuit`: `0.0.2332`
- `@tscircuit/core`: `0.0.1685`
- Byte-1 buses had no `preferredLayer` assignments.
- The focused fanouts completed, but DQ9 and DQ10 exited on `inner2` at the SoC
  and `bottom` at the RAM.
- The published 1.0.7 registry build failed and did not produce a current PCB
  preview.

## After — 2026-08-19

- `tscircuit`: `0.0.2358`
- `@tscircuit/core`: `0.0.1707`
- Core npm `gitHead`: `911a81750403dbc93ddf5d971f952d528a5ec4bd`
- Both breakout paddings: 2 mm
- Autorouter effort: `1x` (the previous `10x` setting exceeded the registry's
  300-second per-file build limit)
- Global autorouter: built-in `beta_pipeline9`
- Global routing is split across the same four byte-1 bus groups to keep each
  capacity-autorouter phase small and deterministic.
- Byte-1 shared bus preferences:
  - DQ9, DQ10: `inner2`
  - DQ11, DQ12, DQ14: `bottom`
  - DQ8, DQ13, DQS1, DQS1_n: `inner3`
  - DQ15, DM1: `inner2`

The same bus declarations are consumed by both breakout autorouting phases, so
each preference applies to the SoC and RAM ends together.

## Verification

- TypeScript: passed
- Netlist: 0 errors, 0 warnings
- Schematic placement: passed
- PCB placement: 0 errors, 0 warnings
- SoC fanout: 11/11 traces, 0 errors
- RAM fanout: 11/11 traces, 0 errors
- Global route: 11/11 traces, 0 autorouter errors
- Fresh cloud-equivalent focused build on `tscircuit@0.0.2358`: passed in
  136.3 seconds
- Layer comparison: 11/11 SoC/RAM pairs matched
- Copper shorts: none detected

The complete route currently reports two via-to-trace clearance diagnostics at
the SoC fanout: 0.004 mm beside DQ9 and 0.021 mm beside DQ15, against the
configured 0.05 mm minimum. Neither is a copper short. This reproduction still
omits the electrical and manufacturing constraints listed in the README and is
not a production DDR layout.