0hmX/am62l-lpddr4-ti-pth-router

README.md

# AM62L32 ↔ LPDDR4 TI-PTH custom router

[Open this new tscircuit project](https://tscircuit.com/0hmX/am62l-lpddr4-ti-pth-router#file=index.circuit.tsx).
The earlier
[`am62l-lpddr4-breakout-repro`](https://tscircuit.com/0hmX/am62l-lpddr4-breakout-repro)
project is separate and is not overwritten by this publication.

This minimal tscircuit project connects exactly 33 direct DDR signals between a
TI AM62L32 (`fccsp_373_anb`) and a Micron MT53E1G16D1ZW LPDDR4 device. Each BGA
is the sole component inside its own sibling `<breakout>`. The traces and buses
live at board scope so every signal crosses both breakout boundaries.

Core automatically creates both sets of breakout points, routes both BGA
fanouts, synchronizes their exits into the parent connections, and then runs the
project-local ordered middle-channel router. The coordinated winding solver
assigns ordered breakout targets and layers; a project-local SRJ-to-SRJ
free-space algorithm routes both BGA fanouts while preserving those exact Core
endpoints.

## Important limitation

This is a 33-signal routing reproduction only. It intentionally omits all DDR
power, ground, decoupling, reference-voltage, termination, impedance, and
timing-signoff requirements. Its breakout geometry uses manufacturing-scale
lands, traces, clearances, and PTH vias, but the reproduction is not a complete
fabrication-ready DDR design.

The DQS0, DQS1, and CK0 differential-pair declarations are temporarily
disabled because the pinned Core expands each pair member into multiple
breakout-local SRJ connections. Those six signals route independently. Their
existing bus order is retained so the coordinated breakout solver can keep each
former pair adjacent where its ordered boundary assignment permits; the custom
fanout solver adds no pair-specific coupling or validation.

## Pinned custom runtime

- `tscircuit`: `0.0.2358`
- bundled `@tscircuit/core`: `0.0.1717`, built from
  [PR #3304](https://github.com/tscircuit/core/pull/3304)
- Core worktree commit: `646a2658a3c3a539e05146a0c9fa468513cbce33`
- bundled artifact: `vendor/tscircuit-core-0.0.1717-pr3304-7453eec0.tgz`
- artifact SHA-256:
  `ff65fd642064eeb0c3058bbd05d4e3fb637245c5ae2ff208e8a1aec69518f4a9`
- `@tsci/tscircuit.ti`: `1.0.100`
- `@tsci/0hmX.mt53e1g16d1zw-footprint`: `1.0.2`

The project uses the bundled archive through a portable relative `file:`
dependency. Run `bun install` after cloning or downloading it. This exact Core
contains the PR #3304 prefactor plus focused changes that preserve a custom
`algorithmFn` through the `fanout` preset and synchronize fanout endpoints and
layers back into the parent SRJ. A registry release of `@tscircuit/core` may not
contain those changes and may not reproduce the 99-trace routed result. See
[`CUSTOM_CORE.md`](CUSTOM_CORE.md) before replacing or rebuilding Core.

## Custom fanout prefactor

`am62l-lpddr4-breakout-circuit.tsx` now exposes independent
`socFanoutAlgorithm`, `ramFanoutAlgorithm`, and `middleChannelAlgorithm`
injection points. The two BGA stages retain Core's `fanout` preset and its
fanout/global endpoint synchronization; the middle stage is deliberately
separate and only joins already-synchronized, same-layer boundary endpoints.
`autorouting/create-in-process-autorouter.ts` supplies the lifecycle adapter for
a synchronous SRJ transform, and `autorouting/am62l-free-space-fanout.ts`
defines the eight reference phases from <https://0hmx.com/>.

The routed prefactor follows TI SPRADI2 breakout geometry: every fanout
transition is a mechanically drilled, full-stack `top`→`bottom` PTH via with a
0.4572 mm pad and 0.2032 mm hole, and the localized fanout trace/space rule is
at least 0.08128/0.08128 mm. Vias may not overlap any BGA land. The project-local
AM62L wrapper uses TI's 0.254 mm copper land with a 0.3048 mm mask opening; the
Micron ZW wrapper uses the CSN-33-derived 0.32 mm NSMD copper land with a
0.40 mm mask opening.

The custom solver derives pad topology, legal local via sites, free-space
regions, 2–3-via strings, target layers, orientation, and buses from each
incoming SRJ. Its boundary-row phase prefers short staggered local dogbones,
then falls back to ordered exterior ViaLines. A bounded conflict-closure search
reassigns only the affected local drops, and every orthogonal corner is replaced
by a clearance-validated 45-degree miter. Both 33-signal packages use the same
geometry algorithm without signal-name or package-coordinate cases.

The board is 90 mm wide. U1/U2 are separated by 40.116917 mm in X; the expanded
fanout bounds are `[-37.377, -2.623]` mm and `[1.381917, 38.851917]` mm, leaving
a 4.004917 mm non-overlapping middle channel.

See `ROUTING_PROMPT.md` for the implementation handoff.

## Commands

```sh
bun install
bun run typecheck
bun run test:prefactor
bun run build
bun run snapshot
bun run build:pcb
bun run verify
bun run verify:byte1-layers
bunx tsci check shorts dist/index/circuit.json
```

`build` (and its `build:pcb` alias) enables PCB SVG/PNG generation plus
autorouter phase diagnostics and records wall-clock time in
`dist/routing-timing.json`. `verify` checks the
structural invariants and writes `dist/verification-report.json` while reporting
all routing and clearance errors without hiding an automatic-routing failure.
`verify:byte1-layers` reads the two fanout phase dumps and fails if any of the
33 signals exits the SoC and RAM breakouts on different layers.

See `RESULTS.md` for the attempted configurations and observed outcome.