0hmX/am62l-lpddr4-clean

This code defines the hardware connections and routing logic for a DDR memory interface, specifying physical signal mappings between the system-on-chip (SoC) and DDR memory components, including connections for data, address, clock, reset, and power/ground balls.

Version: 1.0.0
License: unset
Stars: 0

memory-components.tsx

import { MT53E1G16D1ZW } from "@tsci/0hmX.mt53e1g16d1zw-footprint"
import { AM62L32 } from "@tsci/tscircuit.ti"

export const Soc = () => (
  <AM62L32
    name="U1"
    footprintVariant="fccsp_373_anb"
    noSchematicRepresentation
  />
)

export const Dram = () => (
  <MT53E1G16D1ZW
    name="U2"
    pcbRotation={90}
    noSchematicRepresentation
  />
)