0hmX/am3352

This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.

Version
1.0.5
License
unset
Stars
0

tests/ddr-facing-byte-bus.test.ts

import{test,expect}from'bun:test'
import{facingByteSlots,prepareFacingByteBus}from'../scripts/plan-ddr-facing-byte-bus'
const names=['DM','DQ0','DQ1','DQ2','DQ3','DQ4','DQ5','DQ6','DQ7','DQS_P','DQS_N']
test('right-facing slots preserve an adjacent DQS pair and minimum pitch',()=>{const es=names.map((ramTerminal,i)=>({connection:{ramTerminal,name:`n${i}`},via:{x:0,y:i}})),slots=facingByteSlots(es);expect(slots.length).toBe(11);const p=slots.findIndex(e=>e.connection.ramTerminal==='DQS_P'),n=slots.findIndex(e=>e.connection.ramTerminal==='DQS_N');expect(Math.abs(p-n)).toBe(1);for(let i=1;i<11;i++)expect(slots[i]!.target.y-slots[i-1]!.target.y).toBeCloseTo(.32,9);expect(()=>facingByteSlots(es,.2)).toThrow();expect(()=>facingByteSlots(es,NaN)).toThrow();expect(()=>facingByteSlots(es,Infinity)).toThrow();expect(()=>facingByteSlots(es.map((e,i)=>i?e:{...e,via:{x:NaN,y:0}}))).toThrow()})
test('preparation removes only post-via wires and explicitly invalidates six hosts',()=>{const circuit:any[]=[],connections:any[]=[],obstacles:any[]=[];for(const [i,ramTerminal]of names.entries()){const source_trace_id=`s${i}`,pcb_trace_id=`t${i}`,pointId=`e${i}`,x=-15,y=-10+i*.2;connections.push({name:source_trace_id,source_trace_id,ramByte:0,ramTerminal,pointsToConnect:[{x:-6,y,layer:'inner2',pointId},{x:2,y,layer:'inner2',pointId:`cpu${i}`}]});circuit.push({type:'pcb_breakout_point',pcb_breakout_point_id:pointId,source_trace_id},{type:'pcb_trace',pcb_trace_id,source_trace_id,route:[{route_type:'wire',x,y,layer:'top',width:.12},{route_type:'wire',x:x+.4,y:y+.4,layer:'top',width:.12},{route_type:'via',x:x+.4,y:y+.4,from_layer:'top',to_layer:'inner2'},{route_type:'wire',x:x+.4,y:y+.4,layer:'inner2',width:.12},{route_type:'wire',x:-6,y,layer:'inner2',width:.12}]});obstacles.push({obstacleId:`fixed_trace_${pcb_trace_id}_1_segment`},{obstacleId:`fixed_trace_${pcb_trace_id}_3_segment`},{obstacleId:`fixed_via_${i}`})}const host={traces:Array.from({length:10},(_,i)=>({pcb_trace_id:`host${i}`,connection_name:i<6?`s${i}`:`other${i}`}))},p=prepareFacingByteBus(circuit,{connections},host,obstacles);expect(p.entries.length).toBe(11);expect(p.invalidated.length).toBe(6);expect(p.retained.length).toBe(4);expect(p.removedObstacleIds.length).toBe(11);expect(p.fixedObstacles.length).toBe(22);expect(circuit.filter(e=>e.type==='pcb_trace').every(e=>e.route.length===5)).toBe(true)})