0hmX/am3352

This code suite comprises TypeScript scripts that analyze, verify, and assemble complex DDR memory interface hardware, focusing on physical routing, via and pad placement, electrical clearance, and physical constraints, often involving precise geometric calculations and consistent provenance tracking.

Version
1.0.5
License
unset
Stars
0

scripts/retry-ddr-dq2-shorter.ts

/** Retire exactly the overlong DQ2 host, preserving its proven CPU transition. */
import{readFileSync,writeFileSync,mkdirSync}from'node:fs';import{resolve}from'node:path';import{objectHash as hash}from'./improve-ddr-a9-power-launches';import{auditCompositeHostTopology}from'./ddr-composite-routing-context';import{verifyDdrSystemCopper}from'./check-ddr-system-copper';
const parent=resolve('dist/ddr-twelve-dq1-partial-timing'),out=resolve('dist/ddr-dq2-shorter-parent'),td=resolve('dist/ddr-dq2-shorter-transition'),read=(p:string)=>JSON.parse(readFileSync(p,'utf8')),c=read(parent+'/candidate.circuit.json'),h=read(parent+'/host-bundle.json'),r=read(parent+'/report.json'),input=read(parent+'/routing-input.json'),old=h.traces.find((t:any)=>t.source_trace_id==='source_trace_577'),template=read('dist/ddr-d2-transition/transition-plan.json'),t=template.accepted[0],connection=input.connections.find((c:any)=>c.name===old.connection_name),candidate=c.filter((e:any)=>e.pcb_trace_id!==old.pcb_trace_id),host={...h,traces:h.traces.filter((e:any)=>e.pcb_trace_id!==old.pcb_trace_id)},planes=candidate.filter((e:any)=>e.type==='pcb_copper_pour');
if(hash(c.find((e:any)=>e.pcb_trace_id===old.pcb_trace_id))!==hash(old)||h.traces.length!==12||candidate.length!==c.length-1)throw Error('Unexpected oldDQ2');
const planar=(route:any[])=>route.slice(1).reduce((n:number,p:any,i:number)=>n+(p.route_type==='wire'&&route[i].route_type==='wire'&&p.layer===route[i].layer?Math.hypot(p.x-route[i].x,p.y-route[i].y):0),0),escape=(p:any)=>{const exit=candidate.find((e:any)=>e.pcb_breakout_point_id===p.pointId),ts=candidate.filter((e:any)=>e.type==='pcb_trace'&&e.source_trace_id===exit?.source_trace_id&&e.route.at(-1)?.layer===p.layer&&Math.hypot(e.route.at(-1).x-p.x,e.route.at(-1).y-p.y)<1e-7);if(ts.length!==1)throw Error('Ambiguous escape');return planar(ts[0].route)},[ram,cpu]=[...connection.pointsToConnect].sort((a:any,b:any)=>a.x-b.x),topology=auditCompositeHostTopology(candidate,host.traces,input.connections),ids=new Set(host.traces.map((t:any)=>t.pcb_trace_id)),fixed=candidate.filter((e:any)=>!ids.has(e.pcb_trace_id)),physical=verifyDdrSystemCopper(fixed,[...host.traces,t.trace],input.connections,{});if(!topology.valid||physical.errors.length||physical.violations.length||!physical.angles.valid||physical.joinedBends.length)throw Error('Baseline or CPU transition invalid');
const nominal=read('dist/ddr-integrated-ten/dqlm-audit.json').bytes.find((b:any)=>b.byte===connection.ramByte).dqlmPairedDataMaximumMm,budget={ramEscapeMm:escape(ram),cpuEscapeMm:escape(cpu),nominalMm:nominal,targetPlanarMm:r.strobePair.meanMm};mkdirSync(out,{recursive:true});mkdirSync(td,{recursive:true});const write=(d:string,n:string,v:any)=>writeFileSync(resolve(d,n),JSON.stringify(v,null,2)+'\n');write(out,'candidate.circuit.json',candidate);write(out,'host-bundle.json',host);write(out,'routing-input.json',{...input,traces:host.traces});write(out,'report.json',{...r,candidateCircuitSha256:hash(candidate),physical:topology.physical,topology,exactRetirement:{parentDirectory:parent,parentCircuitSha256:hash(c),before:old,beforeSha256:hash(old)},scope:'Isolated DQ2 reroute experiment;11 hosts retained. Only exact overlong host removed;allplanes preserved.'});write(td,'planes.json',planes);write(td,'transition-plan.json',{captureHash:r.captureHash,parentCircuitSha256:hash(candidate),hostTracesSha256:hash(host.traces),connection,accepted:[{...t,source:cpu,target:ram,budget}],priorTemplateSha256:hash(template),physical});console.log(JSON.stringify({oldHostMm:planar(old.route),oldFullMm:planar(old.route)+budget.ramEscapeMm+budget.cpuEscapeMm,budget,via:t.via,retained:host.traces.length}))