0hmX/am3352

scripts/audit-ddr-global-power-launches.ts

/** Direct RAM-pad launch audit against actual retained traces and final plane contacts. */
import{readFileSync,writeFileSync}from'node:fs'
import{resolve}from'node:path'
const read=(p:string)=>JSON.parse(readFileSync(p,'utf8'))
if(import.meta.main){
 const dir=resolve(process.argv[2]??'dist/ddr-global-plane-reuse-plan'),capture=resolve(process.argv[3]??'dist/ddr-system/host-taps-54af3e346b5e'),circuit=read(`${dir}/candidate.circuit.json`),report=read(`${dir}/report.json`),rows=read(`${capture}/power-drop-audit.json`).rows,result:any[]=[]
 for(const row of rows){
  const join=circuit.find((e:any)=>e.type==='source_trace'&&e.source_trace_id===`planned_ram${row.byte}_${row.ball}_supply`)
  if(!join||join.connected_source_port_ids.length!==1||join.connected_source_net_ids.length!==1)throw Error('Missing explicit RAM rail join')
  const port=circuit.find((e:any)=>e.type==='pcb_port'&&e.source_port_id===join.connected_source_port_ids[0]),pad=circuit.find((e:any)=>e.type==='pcb_smtpad'&&e.pcb_port_id===port?.pcb_port_id)
  if(!pad)throw Error('Missing actual RAM power pad')
  const ts=circuit.filter((e:any)=>e.type==='pcb_trace'&&e.route[0]?.layer===pad.layer&&Math.hypot(e.route[0].x-pad.x,e.route[0].y-pad.y)<1e-7&&circuit.some((s:any)=>s.type==='source_trace'&&s.source_trace_id===e.source_trace_id&&s.connected_source_port_ids.includes(port.source_port_id)))
  if(ts.length!==1)throw Error(`Ambiguous actual power launch ${row.byte}/${row.ball}`)
  const t=ts[0],layer=row.terminal.startsWith('VSS')?'inner1':'inner3',plane=report.planeAudit.find((p:any)=>p.layer===layer),contacts=plane.viaContacts.filter((c:any)=>c.annulusSamplesInPlane===32)
  if(join.connected_source_net_ids[0]!==plane.source_net_id)throw Error('Power pad intended rail differs from plane')
  let length=0,hit:any
  for(let i=1;i<t.route.length&&!hit;i++){const a=t.route[i-1],b=t.route[i];if(a.route_type!=='wire'||b.route_type!=='wire'||a.layer!==pad.layer||b.layer!==pad.layer)continue;const dx=b.x-a.x,dy=b.y-a.y,d=Math.hypot(dx,dy);if(!d)continue;const candidates=contacts.map((v:any)=>({...v,fraction:((v.x-a.x)*dx+(v.y-a.y)*dy)/(d*d)})).filter((v:any)=>v.fraction>=-1e-8&&v.fraction<=1+1e-8&&Math.hypot(v.x-a.x-v.fraction*dx,v.y-a.y-v.fraction*dy)<1e-7).sort((a:any,b:any)=>a.fraction-b.fraction);if(candidates.length)hit={via:candidates[0],lengthMm:length+candidates[0].fraction*d};length+=d}
  result.push({...row,padId:pad.pcb_smtpad_id,pcbTraceId:t.pcb_trace_id,planeId:`planned_global_${layer}`,planeContact:Boolean(hit),actualPadToContactViaMm:hit?.lengthMm??null,connectionVia:hit?.via??null,launchWithin1524Mm:Boolean(hit&&hit.lengthMm<=1.524+1e-8)})
 }
 const output={captureHash:report.captureHash,scope:'Each actual source pad and its source-owned top trace must reach the center of an actual same-rail through via whose full sampled annulus contacts the final continuous plane. Measures centerline distance from pad to that via. Does not qualify impedance or whole PDN.',total:result.length,planeConnected:result.filter(r=>r.planeContact).length,launchQualified:result.filter(r=>r.launchWithin1524Mm).length,unresolved:result.filter(r=>!r.launchWithin1524Mm),rows:result}
 writeFileSync(`${dir}/ram-power-launch-audit.json`,JSON.stringify(output,null,2));console.log(JSON.stringify({...output,rows:undefined,unresolved:output.unresolved.map(r=>`${r.byte}:${r.terminal}`)}))
}