0hmX/am3352

docs/ddr-memory-board-profile.md

# Explicit RAM board-profile wrapper

Current authoritative status and combined clock/ZQ export: [DDR current status](ddr-current-status.md). Earlier experiments below retain their historical scope.

`src/ddr-memory-board-profile.tsx` provides `DdrMemoryBoardProfile`, a portable replacement for invoking the external RAM component with its default host adapter. Its two named profiles load the complete 72-path accepted physical-layer caches without remapping layers or generating reference pours.

```tsx
import { DdrMemoryBoardProfile } from './src/ddr-memory-board-profile'

<board layers={10} allowBlindAndBuriedVias={false}>
  <DdrMemoryBoardProfile
    name="RAM0"
    boardProfile="current_e3_byte0"
    pcbX={-12} pcbY={-6.5} pcbRotation={180}
    connections={{ DQ0: '.CPU .U1 > .DDR_D0', VSSQ_B2: 'net.GND' }}
  />
  <DdrMemoryBoardProfile
    name="RAM1"
    boardProfile="current_e3_byte1"
    pcbX={-12} pcbY={6.5} pcbRotation={180}
  />
</board>
```

The example shows the API, not complete DDR wiring. Every supplied terminal must exist in the frozen pin map. The wrapper preserves the current external component's per-ball net naming, including the B2 ground-anchor name. All other power/ground balls still require explicit host connections. Different module names isolate instance nets.

The generated binding records SHA-256 hashes for the current external API, host adapter, pin map, footprint, reference-plane implementation, accepted circuit, both caches and their contracts. Runtime imports are local; recorded absolute source paths are provenance only. The footprint is an exact copy of the current external footprint, with all78 copper pads, silk and courtyard. The72 routed balls use stable `U1.ball_*` selectors. Source-design omissions are F1, H1, A3, A7 (TDQS_N), F9 and H9; they remain physical pads.

Paths use package-center coordinates and already address the ten-layer physical stack. The wrapper does not accept `hostProfile`, `layerMap`, alternate paths or local-plane options. Via pad/drill dimensions remain0.4572/0.254mm. Use a ten-layer parent with conventional through vias. Cardinal rotations0/90/180/270 preserve the strict45-degree geometry; mirrored/bottom-side mounting is not provided.

These are deliberate board overrides: E1/E2 strobe launches and the CK routes retain the board’s recorded geometry recorded in the accepted caches, even where the current external adapter now emits different geometry. Selecting this wrapper never silently substitutes those new adapter paths.

The bound caches do **not** reproduce the whole accepted board. RAM0 has 22 and RAM1 has 24 additional power-path replacements, enumerated in `additionalBoardCopperOverrides`. Complete board replay also needs those exact replacements, the global planes and rail connectivity, decoupling/support components and host routes. The wrapper is not an assertion that the current external default adapter matches this board profile, nor DDR timing, impedance or fabrication approval.

Regenerate explicitly:

```sh
bun scripts/generate-ddr-memory-board-profiles.ts /path/to/current/ram/project dist/ddr-clock-zq-power59-final
bun test tests/ddr-memory-board-profile.test.tsx
```

Generation verifies the current footprint against all78 pin-map positions/radii, checks full72-path coverage and route angles, binds source files before/after, and records actual board-copper discrepancies. Rendering tests check source-owned ball/exit mapping, every cached point and physical layer, full through-via spans, cardinal transformations, absence of local pours and emitted errors. They do not substitute for the combined board's physical or electrical audits.