0hmX/am3352

docs/ddr-facing-feasibility.md

# Facing escape experiments

These isolated artifacts use frozen capture `host-taps-54af3e346b5e` and the actual `ddr-facing-progress-45` composite. They do not replace the reusable RAM source or constitute DDR timing qualification.

| Experiment | Result on actual composite | RAM / CPU / host lower bound (mm) | Nominal budget (mm) |
| --- | --- | --- | --- |
| D3 exit right, y=-9.3, inner4 | Clear local escape, all eleven existing hosts preserved | 11.002475 / 3.646643 / 11.422465 | 28.899838 |
| DM0 exit right, y=-7.1, planned against older power52 | Rejected: crosses current DQ7 and violates clearance twice | 11.416792 / 3.646643 / 10.842566 | 28.899838 |
| DM0 exit right, y=-7.1, planned against actual composite | Clear local escape, existing DM0 host explicitly retired, ten other hosts preserved and connected | 13.816792 / 3.646643 / 10.842566 | 28.899838 |

All right exits retain x=-6.040077; no envelope padding was added. All experiments retain the existing .4572/.254 mm physical through via and original top pad launch. The accepted local candidates pass full physical clearance, octilinear segments, maximum 45-degree turns, and the independent all-copper junction audit.

The ordered DM0 experiment includes the actual DQ7 local trace as an obstacle. Its DM0 exit is now above DQ7's y=-7.5 exit, consistent with their CPU terminal order. Its optimistic remaining host detour budget is only **0.593837 mm**. A new DM0 host route is still required; the ten-route bundle deliberately excludes its former host trace. Those ten geometrically connected paths still include the independently identified DQ12 topology failure. Downstream routing must also remove DQ12 and use the separately verified nine-path seed; the ten-route candidate is not topology-qualified.

`ram-byte0-ordered-facing.trace-paths.json` contains all 72 RAM0 paths, with 70 unchanged. `exit-contract.json` records B7/DM and E7/DQ7 world-right/local-left exits, physical inner4, world tangent −45° and local tangent 135° at 180° placement. All four sides have zero additional padding, and the original centerline envelope is preserved.

The initial D3 and ordered-DM0 candidates were separate branches from the same composite and were not mutually validated. D3 still needs an inner4-to-inner2 host transition. D5 is the next budget-only candidate: a proposed right exit at y=-8.5 gives an obstacle-free total floor of 25.332043 mm, but no local route has been established and its CPU endpoint is on inner6.

The first D3 escape subsequently failed against the ordered DM0 geometry: three crossings and one 0.08 mm gap to DM0. A single existing-winding attempt using the actual ordered board produced a replacement with RAM length 12.144112 mm and complete planar lower bound **27.213220 mm**, leaving 1.686618 mm below DQLM. `dist/ddr-facing-d3-eleven-host` transplants that replacement onto the later `ddr-dq7-ordered-host` board. All eleven host paths remain exact, connected, and limited to their authorized endpoint contacts. The full physical, angle, junction and local-own-contact checks pass. The local audit allows a contiguous outward departure within the retained via annulus, but rejects re-entry or nonadjacent centerline self-intersections.

That latest D3 artifact contains all 72 RAM0 paths, with B7/DM, E7/DQ7 and C8/DQ3 changed and 69 paths unchanged. Its exit contract documents world-right/local-left C8 at world (-6.040077,-9.3), physical inner4, without increasing the envelope. D3 remains unhosted and needs a transition to its CPU inner2 terminal. This artifact does not include the separate shorter-DQS experiment.

The final compatibility-only merge is `dist/ddr-facing-d3-partial-timing`. It includes the later shortened DQS0 pair and retuned D4/DQ7 host paths from `ddr-dq7-ordered-retuned`, with all eleven host traces unchanged. Full clearance, host endpoint-only contacts, local D3 own contacts, angles and junction checks pass again. The 72-path cache and unchanged envelope are preserved. Exact input file hashes, the four host replacement witnesses and D3 replacement witness are recorded in its report. This is partial byte0 timing progress with an unhosted D3 escape, not complete DDR qualification.

Evidence is under `dist/ddr-facing-d3-feasibility`, `dist/ddr-facing-dm0-order-feasibility`, and `dist/ddr-facing-dm0-ordered-current`. Each experiment records its actual inputs, exact replacement witnesses, preserved/retired hosts, and physical reports. The original planner's implicit via-to-first-wire segment is materialized using the shared `retainViaLaunch` helper before physical validation; moved launches, added vias, and non-octilinear departures are rejected. Targeted tests cover retained geometry and those rejection cases.

Planar length floors exclude obstacle detours, transition delay and reference changes. Byte matching, impedance, return paths, topology and remaining interface routing are still unqualified.