0hmX/am3352

docs/ddr-facing-exit-progress.md

# CPU-facing RAM exit work

Current authoritative status and combined clock/ZQ export: [DDR current status](ddr-current-status.md). Earlier experiments below retain their historical scope.

The original left-facing DM/odd-DQ exits exceeded the placement-derived nominal byte length even before host obstacles. Changing only the host route could not close those budgets. A 90° placement experiment was independently checked and still failed several nominal floors; it is not a substitute for profile work.

## Current integrated RAM exit contracts

`dist/ddr-twenty-one-power59-current` contains both 72-path experimental RAM caches and the twenty-one-host board. RAM0 B7/DM, E7/DQ7, C8/DQ3, C7/DQ1 and E8/DQ5 differ from the frozen cache; E3 also adopts the current adapter launch; the other 66 paths remain exact. All six have connected host routes. Additional padding is zero on every side, and the original path envelope is retained.

| RAM ball / terminal | World exit (mm) | Layer | Local exit (mm) |
| --- | --- | --- | --- |
| B7 / DM | (-6.040077, -7.1) | inner4 | (-5.959923, 0.6) |
| E7 / DQ7 | (-6.040077, -7.5) | inner4 | (-5.959923, 1.0) |
| C8 / DQ3 | (-6.040077, -9.3) | inner4 | (-5.959923, 2.8) |
| C2 / DQ2 (CPU D10) | (-6.040077, 3.185108) | inner4 | E 0° / W 180° |
| C7 / DQ1 | (-6.040077, -8.1) | inner6 | (-5.959923, 1.6) |
| E8 / DQ5 | (-6.040077, -8.5) | inner6 | (-5.959923, 2.0) |
| E3 / DQ4 | (-6.040077, -7.984946) | inner2 | (-5.959923, 1.484946) |

At the frozen 180° RAM placement, all six exit world-right/local-left. DM, DQ7 and DQ3 have final tangent world southeast (-45°), local northwest (135°); DQ1 and E3/DQ4 have final tangent world east (0°), local west (180°). E8/DQ5 has world northeast (45°), local southwest (-135°) tangent. The first five retain their original RAM pad launch and physical through-via, with logical top→inner4 or top→inner6 routing as listed. E3 uses the current relocated full-depth via and logical top→inner2 transition. D3 additionally uses one host through-via at (1.29, -4.8) mm, and DQ1 uses one at (1.29, -1.6) mm, to meet their CPU inner2 exits. The exact per-exit data is in `exit-contract.json`; electrical return-path and full-interface qualification remain incomplete.

RAM1 has seven changed paths (including current E3 and the coupled E7/C2 repair) and 65 unchanged paths, with zero added padding on all sides:

| RAM ball / terminal | World exit (mm) | Layer | World / local tangent |
| --- | --- | --- | --- |
| B7 / DM | (-6.040077, 2.1) | inner2 | NE 45° / SW -135° |
| C7 / DQ1 (CPU D9) | (-6.040077, 3.3) | inner6 | E 0° / W 180° |
| C8 / DQ3 (CPU D11) | (-6.040077, 2.4) | inner6 | NE 45° / SW -135° |
| E7 / DQ7 (CPU D15, connected) | (-6.040077, 4.1) | inner6 | E 0° / W 180° |
| D2 / DQ6 (CPU D14) | (-6.040077, 2.5) | inner2 | E 0° / W 180° |
| E3 / DQ4 (CPU D12, connected) | (-6.040077, 5.015054) | inner4 | E 0° / W 180° |

All RAM1 entries are world-right/local-left; local coordinates and full via-span details are recorded in `ram-byte1-exit-contract.json`. The D11 y=2.9 trial was rejected because its outward collar collided with D9. The accepted y=2.4 exit includes a checked 0.2 mm northeast collar and a connected inner6 host. The current external RAM adapters have changed relative to the frozen capture: see the [current source compatibility caveat](ddr-system-progress.md#current-external-ram-adapter-compatibility) before reuse.

E3 is a launch update on its existing exit contract, not an additional CPU-facing exit listed above. Both bytes add 0.8 mm of local E3 length; byte0 DQ4 host compensation removes 0.8 mm so its complete path stays matched. The [explicit cache envelope audit](../dist/ddr-nineteen-current-e3-metadata-audit/report.json) verifies all 72 paths per byte and unchanged local bounds x −5.959923…5.060050 mm, y −4.800092…5.200092 mm, before and after E3. Added left/right/top/bottom padding is zero. The trace-width/via-radius envelope is also unchanged: x −6.019923…5.120050 mm, y −4.860092…5.428692 mm; unchanged pads and support copper are outside this cache-only measurement. Corrected contract copies in that audit are proposals pending exporter application and hash binding.

The current board has 21 connected signals, 29 missing signals and 59/60 geometrically qualified RAM power launches. The inherited inner3 repair removes two thin copper slivers between existing voids. Its 0.127 mm minimum-web policy and E3's 0.107 mm pour clearance are provisional and do not establish fabrication approval. E1/E2 and clock-adapter differences remain unresolved.

D12's completed path is 22.289882 mm and retains its original RAM escape, adding a host through-via at (−5.5, 5.0) mm. D15 E7 keeps its original launch via, changes its logical destination to inner6, and has a verified 0.2 mm eastward collar against all twenty-one hosts. Its local exit is (−5.959923, 2.4) mm. D15 now connects through a full-depth host via at (1.0, −0.4) mm, logically top↔inner6. Its complete planar length is 23.337480 mm; byte1 matching remains unfinished. The [current cache envelope audit](../dist/ddr-twenty-one-power59-current/cache-envelope-audit.json) includes all cached trace widths and via diameters and proves zero growth relative to the frozen RAM caches. Current contract hashes are bound in the report.

The sections below retain the earlier replacement experiments and their original coordinates for provenance.

## First verified replacement: RAM0 DM / B7

The experimental full 72-path cache is `dist/ddr-facing-dm0-power54/ram-byte0-facing-mask.trace-paths.json`. Only B7 differs from the frozen RAM0 host cache; 71 paths are preserved. The existing top pad-to-via geometry and physical through-via are retained. Its logical destination changes to inner4, matching the CPU DQM0 exit, and new copper travels across the RAM to the CPU-facing edge. No additional padding is needed; the original path envelope contains the new route.

| Contract item | Value |
| --- | --- |
| Local exit side | Left |
| World exit side at the frozen 180° placement | Right, toward CPU |
| World endpoint | (-6.040077, -10.800000) mm |
| Local endpoint | (-5.959923, 4.300000) mm |
| Copper layer | inner4 |
| Outward normal | World (+1, 0), local (-1, 0) |
| Final tangent | World (+√½, -√½), local (-√½, +√½) |
| Existing via | 0.4572 mm pad / 0.254 mm drill; physical barrel spans all ten layers |
| Logical transition | top → inner4 |
| Trace width | 0.12 mm |

The RAM escape is approximately 8.981 mm. Adding the actual CPU escape and an obstacle-free host continuation gives **25.044 mm**, below byte0 DQLM **28.900 mm**. This restores roughly 3.856 mm of optimistic routing margin. The subsequent full-copper host search in `dist/ddr-facing-dm0-host` succeeds: host copper measures 12.785207 mm and the complete RAM + host + CPU planar path measures **25.413042 mm**, leaving 3.486796 mm below that nominal limit. It adds no vias and stays on inner4. The candidate has 11 connected signal nets, zero clearance/angle/join violations, and still requires complete byte timing and propagation-delay validation.

The variant passes against both the original frozen component copper and the combined support board. All ten existing host routes remain connected, and **54/60** RAM power launches remain qualified. Copper clearance, source connections, actual via geometry, strict 45° headings/turns, saved-path schema and unchanged bounds are checked. The assembler rejects any malformed cache. Identical consecutive source-via records returned by the winding solver are coalesced; the exact existing launch and an explicit wire at the via center are retained.

Use `exit-contract.json` for exact coordinates and directions. This cache already uses physical ten-layer names: do not apply the legacy four-layer default remapping. The original interior CA/CK trunk-tap contract remains necessary. A refreshed integration capture and explicit profile-selection API are still needed before this experimental cache can replace the default RAM package profile.

## Rejected alternatives and next scope

Single-layer DM attempts on inner2 failed on both 0.1 mm and 0.05 mm grids with all other copper retained. The fine-grid run exhausted 152,280 states. A joint eleven-signal byte0 experiment removes only declared old post-via paths and invalidates the six affected byte0 host traces in its isolated problem. Its first attempt returned no complete bus; endpoint-center preflights passed, so the remaining connector/reservation restriction needs further diagnosis. Neither attempt replaced the accepted board.

TI's DDR3 guidance does not explicitly require one physical signal layer for an entire byte. Exploring inner4 does not establish stackup approval: immediately adjacent continuous references, impedance, return paths when references change, cross-byte spacing and complete byte timing remain required. See SPRS717L Tables 7-62 and 7-69 and §7.7.2.3.3.7.1. DQ7 also has an isolated inner4 facing escape with a 26.178597 mm optimistic total, below the same nominal limit; its host continuation remains unproven. The other eight nominal-floor-breaking exits remain to be redesigned.

Reproduction:

```sh
bun scripts/plan-ddr-facing-ram-exit.ts dist/ddr-system/host-taps-54af3e346b5e dist/ddr-integrated-ten dist/ddr-integrated-ten-power52 DDR_DQM0 dist/ddr-facing-dm0-inner4 -10.8 .1 inner4
bun scripts/assemble-ddr-facing-exit.ts dist/ddr-system/host-taps-54af3e346b5e dist/ddr-integrated-ten-power54 dist/ddr-facing-dm0-inner4 dist/ddr-facing-dm0-power54
bun scripts/audit-ddr-global-power-launches.ts dist/ddr-facing-dm0-power54
```

All profile variants use the same geometric acceptance rule: horizontal, vertical or diagonal segments at multiples of 45°, and no planar turn greater than 45°. Horizontal and vertical segments are allowed; a direct horizontal-to-vertical corner is not. The same gate applies at joins between saved escapes and host routes. This is a geometric rule, not evidence of electrical DDR qualification.

## DQ3 and ordered-mask experiments

RAM0 DQ3 has a checked facing escape at world (-6.040077,-9.3) mm on inner4, with a 26.071583 mm optimistic total against 28.899838 mm nominal. No additional via or padding is used. This is an escape candidate; its CPU exit is inner2 and a host transition remains to be routed.

The current DM0 and DQ7 exits reverse vertical order between the RAM and CPU on inner4. DQ7 same-layer searches failed at 300,000 and 600,000 states. Moving DM0 upward to y=-7.1 restores port order and passes the nominal floor, but a proposal generated against the older board crossed the revised DQ7 escape. Planning must therefore include the actual composite copper, with the old DM0 host explicitly retired.

The actual-composite ordered variant is now available in `dist/ddr-facing-dm0-ordered-current`. Its full 72-path cache changes only B7/DM and E7/DQ7. DM exits at world (-6.040077,-7.1), local (-5.959923,0.6), and DQ7 at world (-6.040077,-7.5), local (-5.959923,1.0), both on inner4. Both final tangents are world southeast (-45°), local northwest (135°). All four padding changes are zero. The actual RAM mask escape is 13.816792 mm, leaving only 0.593837 mm beyond the obstacle-free host budget; host acceptance remains separate.

The ordered mask host subsequently succeeded in `dist/ddr-dm0-ordered-host`: actual total 28.423158 mm, leaving 0.476680 mm below the nominal limit. It adds no vias and passes strict angles, all-junction checks, conductor clearance and authoritative endpoint-only host contacts. The candidate retains nine prior valid host routes and adds this new mask for ten; DQ12 remains invalidated and DQ7 is still unhosted.

The final compatible D3 candidate is `dist/ddr-facing-d3-partial-timing`. It includes the latest eleven retuned host routes unchanged, and a 72-path RAM cache with B7/E7/C8 changed and 69 preserved. D3 exits at (-6.040077,-9.3) on inner4 and has a 27.213220 mm optimistic total, leaving 1.686618 mm nominal margin before a host transition is routed. Local own-contact, full conductor, angle, junction and host endpoint checks pass. No additional padding or via is used by the escape.

## RAM1 DM1 checked variant

`dist/ddr-twelve-dm1-facing` adds the RAM1 B7/DM1 variant: world-right exit (-6.040077, 2.1) mm, inner2, northeast 45° tangent; local-left exit (-5.959923, 4.4) mm with -135° tangent under the 180° placement. Complete path 22.054969 mm. The 72-path RAM1 cache changes only B7 and adds zero padding on every side. This variant passes full geometry and angle checks but is not complete DDR electrical signoff. Its exit contract is `ram-byte1-exit-contract.json`.

The latest board includes RAM1 F8/E9 and D1 coupled power repairs: 58/60 power launches are qualified geometrically. This adds no host connection or cache padding. See the system progress report for the explicit provisional plane-web assumption.