0hmX/am3352-ddr-track-c-stackup-wip-20261007

routing.tsx

import { Fragment } from "react"
import { ddrSignals } from "./connections"
import { byte0EscapePaths } from "./escapes"
import { autoroutingPhaseProps } from "@tscircuit/props"
import savedPaths from "./data/byte0-saved-paths.json"

const savedNets = new Set(savedPaths.map(p => p.net))
const savedPhase = autoroutingPhaseProps.parse({ name: "C_SAVED_BYTE", phaseIndex: 1,
  autorouter: "single_layer_routing", pcbTracePaths: savedPaths.map(p => ({connection:p.connection,route:p.route})) })

export const byteSignals = (byte: number) => [
  ...Array.from({ length: 8 }, (_, bit) => `DDR_D${byte * 8 + bit}`),
  `DDR_DQM${byte}`, `DDR_DQS${byte}`, `DDR_DQSn${byte}`,
]
const dataSignals = [...byteSignals(0), ...byteSignals(1)]
const addressSignals = ddrSignals.map(signal => signal.net)
  .filter(net => !dataSignals.includes(net) && net !== "DDR_RESETn")

function traceWidth(net: string) {
  const internal = byteSignals(0).includes(net)
  const pair = /DDR_DQSn?\d|DDR_CKn?$/.test(net)
  if (internal) return pair ? 0.101092 : 0.117094
  return pair ? 0.119126 : 0.150876
}

// Published alias normalizes to bus_lanes; no lane-to-lane via fallback.
// Width/gap values come from the live JLC calculator, not an SI measurement.
export function DdrRouting({ route, byte0Only, escapePreview, savedByte = false }: { route: boolean, byte0Only: boolean, escapePreview: boolean, savedByte?: boolean }) {
  const signals = ddrSignals.filter(signal => !byte0Only || byteSignals(0).includes(signal.net))
  return <>
    {savedByte && <autoroutingphase {...savedPhase} />}
    {route && <autoroutingphase name="DDR_SINGLE_LAYER_LANES" phaseIndex={1}
      autorouter="single_layer_routing" />}
    {signals.map(signal => <Fragment key={signal.net}>
      <net name={signal.net} routingPhaseIndex={savedByte && !savedNets.has(signal.net) ? undefined : 1} />
      <trace name={`T_${signal.net}`} width={escapePreview && byteSignals(0).includes(signal.net) ? 0.1016 : traceWidth(signal.net)}
        pcbPathRelativeTo={escapePreview ? `.U1 > .${signal.cpuPin}` : undefined}
        pcbPaths={escapePreview ? byte0EscapePaths(signal.net, signal.cpuPin, signal.ramPin) : undefined}
        routingPhaseIndex={savedByte && !savedNets.has(signal.net) ? undefined : 1} path={[`.U1 > .${signal.cpuPin}`, `.U3 > .${signal.ramPin}`, `net.${signal.net}`]} />
    </Fragment>)}
    {(savedByte || byte0Only ? [0] : [0, 1]).map(byte => <Fragment key={byte}>
      <bus name={`DDR_BYTE${byte}`} routingPhaseIndex={1} connections={byteSignals(byte).map(net => `T_${net}`)}
        maxLengthSkew={0.635} pcbTraceSpacing="3w" pcbSpacingToOtherSignals="4w"
        pcbAllowedLayers={savedByte ? ["inner2", "inner5", "bottom"] : [byte === 0 ? "inner2" : "top"]} />
      <differentialpair name={`DQS${byte}`} positiveConnection={`T_DDR_DQS${byte}`}
        negativeConnection={`T_DDR_DQSn${byte}`} maxLengthSkew={0.127}
        targetDifferentialImpedance={100} pcbTraceGap={0.2032} pcbSpacingToOtherSignals="4w" />
    </Fragment>)}
    {!savedByte && !byte0Only && <>
      <bus name="DDR_ADDRESS_CONTROL" routingPhaseIndex={1} connections={addressSignals.map(net => `T_${net}`)}
        maxLengthSkew={0.635} pcbTraceSpacing="3w" pcbSpacingToOtherSignals="4w"
        pcbAllowedLayers={["bottom"]} />
      <differentialpair name="CK" positiveConnection="T_DDR_CK" negativeConnection="T_DDR_CKn"
        maxLengthSkew={0.127} targetDifferentialImpedance={100}
        pcbTraceGap={0.2032} pcbSpacingToOtherSignals="4w" />
    </>}
  </>
}