0hmX/am3352-ddr-track-a-local-dfm-wip-20261007
Experimental RJ45-corrected board with isolated PG indication. 1005/1005 source joins pass; 15 expanded-guard physical errors, sourcing and qualification gates remain. Not fabrication-ready.
- Version
- 0.0.4
- License
- unset
- Stars
- 0
index.tsx
import { AM3352, pinLabels as cpuLabels } from './components/AM3352'
import { W631GG6MB_12, pinLabels as ramLabels } from './imports/W631GG6MB_12'
import cpu from './data/cpu-connections.json'
import {TimingConstraints} from './design/timing-constraints'
import {Support} from './support'
export const ramNet=(s:string):string|undefined=>{
if(s.startsWith('VSS'))return 'GND'
if(s.startsWith('VDD'))return 'DDR_1V5'
if(s.startsWith('VREF'))return 'DDR_VREF'
if(/^DQL\d/.test(s))return `DDR_D${s.slice(3)}`
if(/^DQU\d/.test(s))return `DDR_D${8+Number(s.slice(3))}`
if(/^A\d+$/.test(s)||/^BA\d/.test(s))return `DDR_${s}`
return ({ODT:'DDR_ODT',CKE:'DDR_CKE',CK:'DDR_CK',N_CK:'DDR_CKn',N_CS:'DDR_CSn0',N_RESET:'DDR_RESETn',N_RAS:'DDR_RASn',N_CAS:'DDR_CASn',N_WE:'DDR_WEn',DML:'DDR_DQM0',DMU:'DDR_DQM1',DQSL:'DDR_DQS0',N_DQSl:'DDR_DQSn0',DQSU:'DDR_DQS1',N_DQSU:'DDR_DQSn1',ZQ:'DDR_ZQ'} as Record<string,string>)[s]
}
export default function Board({ replayAccepted = false }: { replayAccepted?: boolean } = {}){
const cpuConnections=Object.fromEntries(Object.entries(cpuLabels).flatMap(([p,[b]])=>(cpu as any)[b]?[[p,`net.${(cpu as any)[b]}`]]:[]))
const ramConnections=Object.fromEntries(Object.entries(ramLabels).flatMap(([p,[b,s]])=>ramNet(s)?[[p,`net.${ramNet(s)}`]]:[]))
return <board width={98} height={65.5} outline={[{x:-28,y:26.5},{x:70,y:26.5},{x:70,y:-39},{x:-28,y:-39}]} layers={8} thickness={1.2} doubleSidedAssembly routingDisabled schAutoLayoutEnabled={false} minTraceWidth={0.1} minTraceToPadEdgeClearance={0.1} minViaHoleDiameter={0.15} minViaPadDiameter={0.3} title="AM3352 + 10/100 Ethernet + RGB565 TFT — UNROUTED INTERFACE REVISION">
<AM3352 name="U1" pcbX={0} pcbY={0} connections={cpuConnections} noSchematicRepresentation/>
<W631GG6MB_12 name="U3" pcbX={0} pcbY={-27} connections={ramConnections} noSchematicRepresentation/>
<TimingConstraints/>
<Support/>
{/* Original planes/copper are intentionally absent. Route and regenerate all reference planes before release. */}
</board>
}