0hmX/am3352-ddr-track-a-local-dfm-wip-20261007
Experimental RJ45-corrected board with isolated PG indication. 1005/1005 source joins pass; 15 expanded-guard physical errors, sourcing and qualification gates remain. Not fabrication-ready.
- Version
- 0.0.4
- License
- unset
- Stars
- 0
data/cpu-connections.json
{
"F7": "VDD_CORE",
"F6": "VDD_CORE",
"M13": "VDD_CORE",
"J12": "VDD_CORE",
"K12": "VDD_CORE",
"H11": "VDD_CORE",
"M11": "VDD_CORE",
"G10": "VDD_CORE",
"L9": "VDD_CORE",
"K8": "VDD_CORE",
"L8": "VDD_CORE",
"G7": "VDD_CORE",
"L7": "VDD_CORE",
"G6": "VDD_CORE",
"K6": "VDD_CORE",
"L6": "VDD_CORE",
"N13": "VDD_CORE",
"N12": "VDD_CORE",
"N9": "VDD_CORE",
"N8": "VDD_CORE",
"F13": "VDD_MPU",
"F12": "VDD_MPU",
"F11": "VDD_MPU",
"F10": "VDD_MPU",
"G13": "VDD_MPU",
"H13": "VDD_MPU",
"J13": "VDD_MPU",
"A2": "VDD_MPU",
"E5": "DDR_1V5",
"F5": "DDR_1V5",
"G5": "DDR_1V5",
"H5": "DDR_1V5",
"J5": "DDR_1V5",
"K5": "DDR_1V5",
"L5": "DDR_1V5",
"P8": "V3V3",
"P7": "V3V3",
"P11": "V3V3",
"P10": "V3V3",
"P13": "V3V3",
"P12": "V3V3",
"H14": "V3V3",
"J14": "V3V3",
"K14": "V3V3",
"L14": "V3V3",
"F14": "V3V3",
"E13": "V3V3",
"E12": "V3V3",
"E11": "V3V3",
"E10": "V3V3",
"G14": "V3V3",
"P6": "V3V3",
"N5": "V3V3",
"P5": "V3V3",
"N15": "V3V3",
"R15": "V3V3",
"E14": "V1V8",
"F9": "V1V8",
"E6": "V1V8",
"K13": "V1V8",
"P14": "V1V8",
"P9": "V1V8",
"N6": "V1V8",
"D7": "V1V8",
"E9": "V1V8",
"D10": "V1V8",
"E7": "V1V8",
"R10": "V1V8",
"H15": "V1V8",
"R11": "V1V8",
"N16": "V1V8",
"R16": "V1V8",
"A18": "GND",
"A9": "GND",
"B9": "GND",
"C9": "GND",
"A8": "GND",
"B8": "GND",
"C8": "GND",
"D8": "GND",
"E8": "GND",
"F8": "GND",
"A7": "GND",
"B7": "GND",
"C7": "GND",
"B6": "GND",
"A5": "GND",
"A1": "GND",
"M14": "GND",
"L13": "GND",
"G12": "GND",
"H12": "GND",
"L12": "GND",
"M12": "GND",
"G11": "GND",
"J11": "GND",
"K11": "GND",
"L11": "GND",
"H10": "GND",
"J10": "GND",
"K10": "GND",
"L10": "GND",
"M10": "GND",
"G9": "GND",
"H9": "GND",
"J9": "GND",
"K9": "GND",
"M9": "GND",
"G8": "GND",
"H8": "GND",
"J8": "GND",
"M8": "GND",
"H7": "GND",
"J7": "GND",
"K7": "GND",
"M7": "GND",
"H6": "GND",
"J6": "GND",
"M6": "GND",
"V18": "GND",
"N14": "GND",
"N11": "GND",
"V11": "GND",
"N10": "GND",
"N7": "GND",
"V1": "GND",
"C6": "PMIC_POWER_EN",
"B15": "PWRONRST_N",
"A10": "WARMRST_N",
"B5": "RTC_RESET_N",
"B4": "RTC_KALDO_EN_N",
"D6": "CAP_VDD_RTC",
"D9": "CAP_VDD_SRAM_CORE",
"D11": "CAP_VDD_SRAM_MPU",
"C10": "CAP_VBB_MPU",
"C17": "I2C0_SDA",
"C16": "I2C0_SCL",
"V8": "PMIC_INT_N",
"C5": "EXT_WAKEUP",
"L3": "DDR_D13",
"M1": "DDR_D15",
"K4": "DDR_D12",
"L2": "DDR_DQSn1",
"L4": "DDR_D14",
"K3": "DDR_D11",
"K1": "DDR_D9",
"L1": "DDR_DQS1",
"K2": "DDR_D10",
"J2": "DDR_DQM1",
"J1": "DDR_D8",
"M3": "DDR_D0",
"M2": "DDR_DQM0",
"N1": "DDR_D2",
"P1": "DDR_DQS0",
"M4": "DDR_D1",
"N2": "DDR_D3",
"P3": "DDR_D6",
"P2": "DDR_DQSn0",
"N3": "DDR_D4",
"P4": "DDR_D7",
"N4": "DDR_D5",
"G4": "DDR_RASn",
"D2": "DDR_CK",
"G1": "DDR_ODT",
"F1": "DDR_CASn",
"D1": "DDR_CKn",
"G3": "DDR_CKE",
"H2": "DDR_CSn0",
"B2": "DDR_WEn",
"F4": "DDR_A10",
"C4": "DDR_BA0",
"B3": "DDR_BA2",
"C3": "DDR_A3",
"F3": "DDR_A0",
"E3": "DDR_A12",
"E1": "DDR_BA1",
"B1": "DDR_A5",
"E4": "DDR_A2",
"H1": "DDR_A1",
"C2": "DDR_A4",
"E2": "DDR_A7",
"C1": "DDR_A9",
"F2": "DDR_A11",
"D5": "DDR_A6",
"G2": "DDR_RESETn",
"D4": "DDR_A8",
"J4": "DDR_VREF",
"J3": "DDR_VTP",
"R1": "SYSBOOT0",
"R2": "SYSBOOT1",
"R3": "SYSBOOT2",
"R4": "SYSBOOT3",
"T1": "SYSBOOT4",
"T2": "SYSBOOT5",
"T3": "SYSBOOT6",
"T4": "SYSBOOT7",
"U1": "SYSBOOT8",
"U2": "SYSBOOT9",
"U3": "SYSBOOT10",
"U4": "SYSBOOT11",
"V2": "SYSBOOT12",
"V3": "SYSBOOT13",
"V4": "SYSBOOT14",
"T5": "SYSBOOT15",
"V10": "SOC_CLK24",
"E16": "UART0_TX",
"E15": "UART0_RX",
"G17": "MMC0_CLK",
"G18": "MMC0_CMD",
"G16": "MMC0_DAT0",
"G15": "MMC0_DAT1",
"F18": "MMC0_DAT2",
"F17": "MMC0_DAT3",
"U10": "MMC0_CD_N",
"C11": "TMS",
"A12": "TCK",
"A11": "TDO",
"B11": "TDI",
"B10": "TRST_N",
"C14": "EMU0",
"B14": "EMU1",
"H17": "RMII1_CRS_DV",
"H18": "RMII1_REFCLK",
"M16": "RMII1_RXD0",
"L15": "RMII1_RXD1",
"J15": "RMII1_RX_ER",
"K17": "RMII1_TXD0",
"K16": "RMII1_TXD1",
"J16": "RMII1_TX_EN",
"M17": "ETH_MDIO",
"M18": "ETH_MDC",
"V5": "LCD_PCLK",
"R6": "LCD_DE",
"V13": "LCD_OUTPUT_ENABLE",
"V14": "LCD_STBY",
"C18": "LCD_BL_PWM"
}