0hmX/am3352-ddr-track-a-local-dfm-wip-20261007

authoring/PG-ELECTRICAL-AND-ASSEMBLY.md

# Independent PG indicator: electrical and assembly evidence

The previous v6 LED takes its input from OSC24_OE and operates its inverter at V1V8. Its undefined logic below 1.65 V and long OE/SYSBOOT7 exposure remain unacceptable as a qualified debug addition. V7 instead senses PMIC_PGOOD through 100 kΩ, shunts that sense node to GND with 100 kΩ, and powers a local Schmitt inverter from V3V3. There is no new OE or V1V8 branch. The original PG/reset/clock circuit is preserved.

The new driver's pin 1 is NC, 2 sense A, 3 GND, 4 LED cathode Y and 5 V3V3. A 100 nF bypass spans its supply. V3V3 supplies the APT1608SGC anode through 1 kΩ; 10 kΩ shunts the LED. PGOOD high makes Y low and lights the LED after the local supply is valid. It indicates the TPS65216's monitored, enabled DCDC1–4/LDO1 outputs, not every board rail or successful firmware execution.

The [TI SN74AUP1T14 datasheet](https://www.ti.com/lit/ds/symlink/sn74aup1t14.pdf), saved with its retrieval receipt, guarantees VT+ ≤1.19 V and VT− ≥0.5 V over −40 to +85 °C at VCC 3.0–3.6 V. Its recommended VCC range starts at 2.3 V; no threshold interpolation is assumed for 2.7–3.0 V. The Schmitt input accepts slow edges. The 0.5 µA input-current table explicitly tests VI=3.6 V or GND; the static divider model uses that limit but does not turn it into an independently characterized intermediate-voltage current guarantee. The startup loading bound does not use this leakage limit or a defined output state. Table units were checked visually: the low-current rows are µA, despite plaintext extraction errors.

The [bounded calculation](electrical-bounds.json) accepts V3V3 3.0–3.6 V, the original nominal 10 kΩ pull-up within 8–12 kΩ, original powered 1.8 V receivers at 1.65–1.95 V, and −40 to +85 °C. New Yageo F resistors use 1% plus 100 ppm/K ×65 K worst tolerance. For a 0–3.6 V signal and an adverse sense clamp at −0.5 V, the series branch draws at most **41.688 µA**, independent of gate behavior. With 20.5 µA old powered-off leakage, the minimum PGOOD high is **2.400 V**, leaving at least **0.300 V** above the existing TPS3808 MR threshold. Total low-state sink is **0.553 mA**, below the [TPS65216](https://www.ti.com/lit/ds/symlink/tps65216.pdf) 2 mA functional VOL test. The separate −0.5–4.6 V input absolute-stress screen allows 46.772 µA and 0.558 mA total low sink; it is a stress screen, not an operating guarantee.

At valid nominal 3.3 V, the conditional static model gives sense high ≥1.307 V and low ≤0.2283 V. Even a shorted LED draws ≤3.661 mA through its series resistor, below the 4 mA recommended sink at 3 V. The driver's −20 µA VOH row permits a 0.1 V drop; the 1 kΩ/10 kΩ off load is ≤9.244 µA. The shunt reduces off-state LED voltage, but no zero-light or brightness guarantee is asserted.

The [TPS3808](https://www.ti.com/lit/ds/symlink/tps3808.pdf) MR threshold is 0.7 VDD; its 70 kΩ minimum internal pull-up assists the high state and is included in the low-state sink screen. Source pins 5/6 of U_RESET_DELAY were directly checked as V3V3. Existing 1.8 V receiver under-voltage behavior, original PGOOD slew and actual power/boot settings remain inherited gates. V7 removes the known added OE dependency; it does not certify all board boot sequences. Its LED output can be undefined below 2.3 V, in the unqualified threshold band, or during a local ramp. Bench startup/flash, optical visibility, intermediate input behavior and original PG edge acceptance are still required.

| References | Exact MPN / JLCPCB assembly ID | Stock at 2026-10-07 14:57 UTC |
| --- | --- | ---: |
| U_PG_LED | SN74AUP1T14DCKR / C2682010 | 2310 |
| R_PG_SENSE, R_PG_PULLDOWN | RC0402FR-07100KL / C60491 | 9133441 |
| D_PG_LED | APT1608SGC / C5875754 | 11878 |
| R_PG_LED | RC0402FR-071KL / C106235 | 2432169 |
| R_PG_LEAK | RC0402FR-0710KL / C60490 | 10572387 |
| C_PG_LED | GRM155R71C104KA88D / C71629 | 1137062 |

[Exact per-part assembly receipts](evidence/refresh-final/) report `assemblyMode=smtWeld`, `componentLibraryType=expand` and nonzero `overseasStockCount`; this is official JLCPCB assembly SSR data, not an LCSC listing or presale inventory. The driver/passives are MSL1 and LED MSL3. Product type is preserved as numeric 0 without inventing an enum label. No stock is reserved.

TI's DCK0005A example drawing 4214834/G (11/2024) uses five 0.95×0.4 mm lands, rows centered at ±1.1 mm and 0.65 mm pitch. V7 uses those dimensions, pin numbering and all-bottom pads, with 0.07 mm NSMD mask expansion and paste enabled. Its conservative package envelope includes up to 0.15 mm flash/protrusion per side: 1.7×2.45 mm before rotation, enlarged to include land bounds for placement screening. The rectangle lands omit the example's R0.05 corners; this alternate corner detail and mask/process tolerances remain assembly acceptance items.

The exact Yageo 0402 example uses 0.6 mm square lands with 0.5 mm gap. Murata's exact GRM155 specification reflow example uses 0.4×0.5 mm lands with 0.4 mm gap. Kingbright's exact APT1608SGC example uses 0.8 mm square lands with 0.85 mm gap; pin 1 is cathode. The saved manufacturer PDFs/receipts, TSX and native pad comparison document compatibility. Native supply/net/pin correspondence passes, but paste, mask registration, CPL zero orientation and assembly-process acceptance remain unqualified. These new-part findings do not close the ongoing original RAM/CPU/PMIC/PHY and full BOM audit.