0hmX/am3352-ddr-track-a-local-dfm-wip-20261007

README.md

# Track A — experimental RJ45-corrected PCB preview

**Experimental RJ45-corrected board with isolated PG indication. 1005/1005 source joins pass; 15 expanded-guard physical errors, sourcing and qualification gates remain. Not fabrication-ready.**

This owner-approved immutable snapshot at `56fd6bb5bffcf63ae4460fee272968ed374b7be6` supersedes the earlier PG-v6 preview. It includes the isolated seven-part PG indicator, checked remote-via and plane changes, RAM courtyard and CPU mask corrections, and the Würth 7499010121A shield-hole spacing correction from 15.80 to 16.00 mm. All 1005/1005 required source joins and 1,233 terminal bindings pass. The saved board has 328 components, 1,190 trace records, 1,072 vias and 77 pours. DDR signal copper remains preserved. Source and native checks retain zero added error pairs for the checked changes; the expanded guard still has 15 physical errors. This is not a clean full-board DRC or manufacturing release.

The new PG circuit uses an isolated resistive PGOOD input and adds no OSC24_OE or V1V8 branch. The obsolete v6 circuitry is excluded. PG intermediate-input behavior, optical startup, board reset/slew and firmware sequencing remain bench gates. The RJ45 nominal shield-hole spacing is corrected; connector fit and process tolerances remain unqualified.

The default public PCB and hosted viewer use the exact saved `routed/circuit.json`: SHA-256 `4ed4c784f20a492ac5736e026cdc62ce9ed35da8656c6f70c9132ef3be7e9700`, 11,552 records, 54,152,414 bytes. The build reconstructs the frozen bytes, exports a viewer directly from JSON, verifies every exported record and preserves exact bytes in `dist/routed/circuit.json`. Routing is disabled and no source compilation or rerouting occurs during publication. Run `bun scripts/reconstruct.mjs` after cloning to recover that exact JSON.

Original `index.tsx` and its local authored dependencies remain unchanged. `src-pg-v7/` preserves the isolated PG module and placement plan. `authoring/rj45-footprint-delta.json` and `authoring/RJ45_7499010121A.json` declare the two corrected shield-hole coordinates without silently changing the original source library. The original routing-disabled 316-part source and separate PG module do not regenerate the saved 328-part routed board. The static routed JSON is the authoritative complete PCB. File and source bindings are recorded in `frozen-preview-manifest.json`; local checks also verified all 203 owner-frozen handoff files.

## Remaining engineering gates

Eight assigned drill relations and seven additional unchanged RXD0 relations remain in the expanded clearance guard; full-board DRC, fills and manufacturing tolerances remain open.

Exact current PMIC source identity/land pattern, zero-stock RTC supervisor and Ethernet oscillator remain unresolved. Stocked passive and other replacements need electrical, land, bias, stability and assembly review.

CPU assembly-library rotation/CPL, inherited land deviations, solder-mask registration, stencil, complete native DRC/refill and manufacturing tolerances remain open. RJ45 nominal hole spacing is corrected; connector fit/process tolerances remain unqualified.

PG isolated-input loading bounds are documented; intermediate input behavior, optical startup, board reset/slew and actual firmware sequencing need bench qualification.

Global DDR model adequacy failed. No verified DDR eye/crosstalk improvement. Six approval-denied Palace cases were not restarted.

The proposed stack is JLC08121H-3313, finished 1.18 mm ±10%. The original physical stack remains unknown and legacy fine vias are unconverted. Stock receipts are dated evidence, not current procurement commitments; proposed substitutes are unqualified and were not applied by this publication. No purchases, orders or merges are part of this preview.

The original b28 baseline remains unchanged at https://tscircuit.com/0hmX/am3352-ethernet-rgb-b28-987. This is an experimental review copy, not fabrication-ready.